Vivado includes logic analyzer tools for design verification and debugging. Configure and implement IP debug cores, such as the integrated logic analyzer (ILA) and debug hub core, in RTL or synthesized netlists. Open a synthesized or implemented design to select and configure the required probe signals for the cores.
Launch the Vivado logic analyzer on any run with a completed bitstream for interactive hardware verification. Generate programming bitstreams for completed implementation runs, adjusting file generation options as needed. Use theVivado device programmer to configure and program the target part.
You can launch the Vivado logic analyzer directly from the Vivado IDE for detailed routing or device resource analysis. For more information, refer to the Vivado Design Suite User Guide: Programming and Debugging (UG908).