You can use the Vivado Design Suite to analyze, verify, and modify your design at each stage of the design process. Run design rule and design methodology checks, logic simulation, timing analysis, and power analysis to improve circuit performance. Perform these analyses after RTL elaboration, synthesis, and implementation. For details, refer to the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
The Vivado simulator lets you run behavioral and structural logic simulation at different stages of the design flow. The simulator supports mixed-mode Verilog and VHDL simulation, displaying results in a waveform viewer integrated into the Vivado IDE. You can also integrate and launch third-party simulators from the Vivado IDE. For more information, refer to Running Logic Simulation.