The Vivado Design Suite supports different project types for different design purposes. For example, you can create a project with RTL sources or synthesized netlists from third-party providers. You can also create empty I/O planning project for device exploration and early pin planning. The Vivado IDE displays only the commands relevant to the selected project type.
In the Vivado IDE, the Create Project wizard guides you through project creation. You define the project name, storage location, project type, and target part. You can add the following sources such as:
- RTL
- IP
- Block designs
- XDC or SDC constraints
- Simulation test benches
- DSP modules from System Generator
- Vivado High-Level Synthesis (HLS)
- Design documentation
You can choose whether to reference sources in their original location or to copy them into the project directory. Vivado tracks the time and date stamp of each file and its report status, alerting you to out-of-date sources or design statuses. For more details, refer to the Vivado Design Suite User Guide: System-Level Design Entry (UG895).