The Vivado IP integrator lets you create block designs (.bd), or IP subsystems, stitching multiple IP together using the AXI4 interconnect protocol. You can quickly connect IP cores to build domain-specific subsystems and designs, including embedded processor-based designs using AMD Zynq™ UltraScale+™ MPSoC, AMD Zynq™ 7000 SoC, and MicroBlaze™ processors.
The Vivado IP integrator can instantiate high-level synthesis (HLS) modules from Vivado HLS, DSP modules from System Generator, and custom user-defined IP. Refer to Packaging Custom IP and IP Subsystems for details.
With Vivado IP integrator, you can drag IP onto the design canvas. Connect AXI interfaces with a single wire, and place ports or interface ports to connect the IP subsystem to the top-level design. You can package these IP block designs as .bd source files and reuse them in other projects. For details, refer to the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) or MicroBlaze Processor Embedded Design User Guide (UG1579).