The following table defines timing constraints for various signal groups and their targets, similar to how they would be entered into PCB layout software tools. Adaptive SoC package delays should always be included for purposes of determining skews.
| Skew Constraint 1 | Pin Pair Set | Minimum (ps) | Maximum (ps) | Group | Target |
|---|---|---|---|---|---|
| Address to Clock A | Adaptive SoC to LPDDR5 Device | –50 | +50 | CA[6:0]_A | CK_T_A |
| Address to Clock B | Adaptive SoC to LPDDR5 Device | –50 | +50 | CA[6:0]_B | CK_T_B |
| Command to Clock A | Adaptive SoC to LPDDR5 Device | –20 | +20 |
CS0_A CS1_A 5 |
CK_T_A |
| Command to Clock B | Adaptive SoC to LPDDR5 Device | –20 | +20 |
CS0_B CS1_B 5 |
CK_T_B |
| Clock A 2 | Adaptive SoC to LPDDR5 Device | 0 | 2 |
CK_T_A CK_C_A |
– |
| Clock B 2 | Adaptive SoC to LPDDR5 Device | 0 | 2 |
CK_T_B CK_C_B |
– |
| Data to WCK0_A | Adaptive SoC to LPDDR5 Device | –50 | +50 |
DQ[7:0]_A DMI0_A |
WCK0_T_A |
| Data to WCK1_A | Adaptive SoC to LPDDR5 Device | –50 | +50 |
DQ[15:8]_A DMI1_A |
WCK1_T_A |
| Data to WCK0_B | Adaptive SoC to LPDDR5 Device | –50 | +50 |
DQ[7:0]_B DMI0_B |
WCK0_T_B |
| Data to WCK1_B | Adaptive SoC to LPDDR5 Device | –50 | +50 |
DQ[15:8]_B DMI1_B |
WCK1_T_B |
| Data to RDQS0_A | Adaptive SoC to LPDDR5 Device | –50 | +50 |
DQ[7:0]_A DMI0_A |
RDQS0_T_A |
| Data to RDQS1_A | Adaptive SoC to LPDDR5 Device | –50 | +50 |
DQ[15:8]_A DMI1_A |
RDQS1_T_A |
| Data to RDQS0_B | Adaptive SoC to LPDDR5 Device | –50 | +50 |
DQ[7:0]_B DMI0_B |
RDQS0_T_B |
| Data to RDQS1_B | Adaptive SoC to LPDDR5 Device | –50 | +50 |
DQ[15:8]_B DMI1_B |
RDQS1_T_B |
| WCK0_A 2 | Adaptive SoC to LPDDR5 Device | 0 | 2 |
WCK0_T_A WCK0_C_A |
– |
| WCK1_A 2 | Adaptive SoC to LPDDR5 Device | 0 | 2 |
WCK1_T_A WCK1_C_A |
– |
| WCK0_B 2 | Adaptive SoC to LPDDR5 Device | 0 | 2 |
WCK0_T_B WCK0_C_B |
– |
| WCK1_B 2 | Adaptive SoC to LPDDR5 Device | 0 | 2 |
WCK1_T_B WCK1_C_B |
– |
| RDQS0_A 2 | Adaptive SoC to LPDDR5 Device | 0 | 2 |
RDQS0_T_A RDQS0_C_A |
– |
| RDQS1_A 2 | Adaptive SoC to LPDDR5 Device | 0 | 2 |
RDQS1_T_A RDQS1_C_A |
– |
| RDQS0_B 2 | Adaptive SoC to LPDDR5 Device | 0 | 2 |
RDQS0_T_B RDQS0_C_B |
– |
| RDQS1_B 2 | Adaptive SoC to LPDDR5 Device | 0 | 2 |
RDQS1_T_B RDQS1_C_B |
– |
| WCK0_A to Clock A | Adaptive SoC to LPDDR5 Device | –50 | +50 | WCK0_T_A | CK_T_A |
| WCK1_A to Clock A | Adaptive SoC to LPDDR5 Device | –50 | +50 | WCK1_T_A | CK_T_A |
| WCK0_B to Clock B | Adaptive SoC to LPDDR5 Device | –50 | +50 | WCK0_T_B | CK_T_B |
| WCK1_B to Clock B | Adaptive SoC to LPDDR5 Device | –50 | +50 | WCK1_T_B | CK_T_B |
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