Timing Constraint Rules for DDR5 Signals

Timing Constraint Rules for DDR5 Signals - UG863

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID

UG863

Release Date

2025-03-04

Revision

1.9 English

The timing constraints are defined in the following tables for various signal groups and their targets, similar to how they would be entered into PCB layout software tools. Adaptive SoC package delays should always be included for purposes of determining skews.

Table 1. Skew Constraint Rules for DDR5 Signals
Skew Constraint¹	Pin Pair Set	Minimum (ps)	Maximum (ps)	Group	Target
Command/Address/Control to Clock²	Adaptive SoC to DDR5 component/DIMM	–50	+50	CA[13:0] CS_N	CK_T
Clock^{2, 3}	Adaptive SoC to DDR5 component/DIMM	0	2	CK_T CK_C	–
Data to DQS⁴	Adaptive SoC to DDR5 component/DIMM	–50	+50	DQ (4/8 bits) DM_N	DQS_T
DQS^{3, 4}	Adaptive SoC to DDR5 component/DIMM	0	2	DQS_T DQS_C	–
Clock to DQS⁴ (Components)	Adaptive SoC to DDR5 component	–149	+1796	CK_T	DQS_T
Clock to DQS⁴ (DIMM)	Adaptive SoC to DDR5 DIMM	–150	+150	CK_T	DQS_T
LBDQ to LBDQS	Adaptive SoC to DDR5 Component/DIMM	-50	+50	LBDQ_LBDQS	LBDQS
Include adaptive SoC package delays for all skew calculations. There should be individual constraint sets for each DDR5 component/DIMM (for example, adaptive SoC to DRAM1, adaptive SoC to DRAM2, etc.). It does not matter which signal is faster or slower, but the difference in time between the two should be no longer than specified. There should be individual constraint sets for each byte/nibble/DQS pair.