The required signals used in LPDDR5/5x applications are shown in the following table.
| Signal | Description | Required PCB Termination |
|---|---|---|
| Clock Signals | ||
| CK_T[C]_A, CK_T[C]_B | Address/Command clock | None, uses ODT 40Ω |
| Command/Address Signals | ||
| CA[6:0]_A, CA[6:0]_B | Address | None, uses ODT 40Ω |
| Control Signals | ||
| CS0_A, CS0_B | Chip Select | 240Ω to GND |
| CS1_A, CS1_B | Chip Select (dual rank only) | 240Ω to GND |
| Data Signals | ||
| DQ[15:0]_A, DQ[15:0]_B | Data | None, uses ODT 40Ω |
| DMI[1:0]_A, DMI[1:0]_B | Data Mask Inversion | None, uses ODT 40Ω |
| Data Clock Signals | ||
|
WCK[1:0]_T[C]_A, WCK[1:0]_T[C]_B |
Differential Data Clocks | None, uses ODT 40Ω |
| Read Data Strobe Signals | ||
| RDQS[1:0]_T[C]_A, RDQS[1:0]_T[C]_B | Differential Read Data Strobe | None, uses ODT 40Ω |
| Miscellaneous Signals | ||
| RESET_n | Reset (one per LPDDR5/5x device) | 4.99 kΩ to GND |
| LPDDR5/5x Device Only | ||
| ZQ, ZQ_A | Calibration Reference (per device) | 240Ω to VDDQ |
| Adaptive SoC Only | ||
|
IO_VR_7xx IO_VR_8xx (if present) |
Calibration Reference |
240Ω to VCCO_7xx 240Ω to VCCO_8xx (if present) |
Supply Voltages for LPDDR5/5x
| Power Rail | Voltage |
|---|---|
| Adaptive SoC VCCO | 1.0 |
| LPDDR5/5x VDDQ | 0.5 |
| LPDDR5/5x VDD1 | 1.8 |
| LPDDR5/5x VDD2H/VDD2L (Single Core Power Rail) | 1.05 |
|
|
The following figures show the various supported connection options for LPDDR5/5x such as 1x16 single/dual rank, 2x16 single/dual rank, and 1x32 single/dual rank.
Figure 1. LPDDR5/5x 1x16 Single/Dual Rank
Figure 2. LPDDR5/5x 2x16 Single/Dual Rank
Figure 3. LPDDR5/5x 1x32 Single/Dual Rank
