The required signals used in DDR5 applications are shown in the following table. The signal list might vary slightly depending on the particular DDR5 architecture used.
| Signal | Description | Required PCB Termination |
|---|---|---|
| Clock Signals | ||
| CK_T/C | Address/Command clock | None, uses ODT to 40Ω |
| Command/Address Signals | ||
| CA[13:0] | Address | None, uses ODT to 40Ω |
| Control Signals | ||
| CS_N | Chip Select | None, uses ODT to 40Ω |
| LBDQ | DQ Loopback (calibration) | None, uses ODT to 40Ω |
| LBDQS | DQS Loopback (calibration) | None, uses ODT to 40Ω |
| Data Signals | ||
| DQ[n:0] | Data | None, uses ODT to 40Ω |
| DM_N | Write Data Mask | None, uses ODT to 40Ω |
| Data Strobe Signals | ||
| DQS_T/C[n:0] | Differential Data Strobe | None, uses ODT to 40Ω |
| Miscellaneous Signals | ||
| RESET_n | Reset | 4.7 kΩ to GND (at end of fly-by when using multiple devices) |
| DDR5 Device Only | ||
| CAI | Command Address Invert | Connect direct to GND |
| CA_ODT | Command/Address ODT | For flyby, direct to ground for all devices except for last device which should be tied directly to VDDQ |
| MIR (clamshell) | CA Mirror |
Direct to GND (standard mode) Direct to VDDQ (mirrored mode) |
| MIR (non-clamshell) | CA Mirror | Direct to GND |
| TEN | Connectivity Test Mode | Connect direct to GND |
| ZQ | Calibration Reference (per device) | 240Ω to GND |
| Adaptive SoC Only | ||
|
IO_VR_7xx IO_VR_8xx (if present) |
Calibration Reference |
240Ω to VCCO_7xx 240Ω to VCCO_8xx (if present) |