The required signals used in DDR5 applications are shown in the following table. The signal list might vary slightly depending on the particular DDR5 architecture used.
| Signal | Description | Required PCB Termination |
|---|---|---|
| Clock Signals | ||
| CK_T/C | Address/Command clock | None, uses ODT to 40 Ω |
| Command/Address Signals | ||
| CA[13:0] | Address | None, uses ODT to 40 Ω |
| Control Signals | ||
| CS_N | Chip Select | None, uses ODT to 40 Ω |
| LBDQ | DQ Loopback (calibration) | None, uses ODT to 40 Ω |
| LBDQS | DQS Loopback (calibration) | None, uses ODT to 40 Ω |
| PAR_A, PAR_B (DIMMs) | Command/Address Parity | None, uses ODT to 40 Ω |
| Data Signals | ||
| DQ[n:0] | Data | None, uses ODT to 40 Ω |
| DM_N | Write Data Mask | None, uses ODT to 40 Ω |
| Data Strobe Signals | ||
| DQS_T/C[n:0] | Differential Data Strobe | None, uses ODT to 40 Ω |
| Miscellaneous Signals | ||
| ALERT_N (components) | CRC Error Flag Open-Drain Output | Connect ALERT_N pins as flyby and terminate to VDDQ with a 50 Ω resistor |
| ALERT_N (DIMMs) | CRC Error Flag Open-Drain Output | None Note: If the DDRMC
contains two ALERT_N pins, connect them both to the ALERT_N pin
of the DIMM.
|
| RESET_n | Reset | 4.7 kΩ to GND (at end of fly-by when using multiple devices) |
| DDR5 Device/DIMM Only | ||
| CAI | Command Address Invert | Connect direct to GND |
| CA_ODT | Command/Address ODT | When multiple components are used in fly-by routing: Direct to ground for all devices except the last which is tied directly to VDDQ |
| HSA, HSCL, HSDA (DIMM) | Host Sideband Signals | Connect as required in system (see JEDEC specification). A level shifter might be required depending on the source voltage 1 . |
| MIR (clamshell) | CA Mirror |
Direct to GND (standard mode) Direct to VDDQ (mirrored mode) |
| MIR (non-clamshell) | CA Mirror | Direct to GND |
| PCAMP | Control and Monitor Port | Has three possible functions (see JEDEC specification) |
| PWR_EN/POWER_GOOD (DIMM) | Power Good (Open Drain)/PMIC Enable | Connect as required in system (see JEDEC specification) |
| TEN | Connectivity Test Mode | Connect direct to GND |
| VIN_BULK (DIMMs) | PMIC Analog power input supply | 12V (RDIMM) 5V (UDIMM) |
| VIN_MGMT (RDIMM) | Management Supply Voltage | 3.3V (RDIMM) |
| ZQ | Calibration Reference (per device) | 240 Ω to GND |
| Adaptive SoC Only | ||
|
IO_VR_7xx IO_VR_8xx (if present) |
Calibration Reference |
240 Ω to VCCO_7xx 240 Ω to VCCO_8xx (if present) |
|
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