Physical Design Rules for RLDRAM3 Signals - Physical Design Rules for RLDRAM3 Signals

Physical Design Rules for RLDRAM3 Signals - Physical Design Rules for RLDRAM3 Signals - UG863

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID

UG863

Release Date

2026-02-20

Revision

1.11 English

The following table defines routing rules for RLD3 signals.

Table 1. Physical Design Rules for RLD3 Signals
Parameter	Value
Impedance Rules
Impedance for single-ended address/command/control and data signals	50 Ω¹± 10%
Impedance for differential clock (CK), data write clock (DK), and data read clock (QK)	90 Ω¹± 10%
Maximum Trace Length Rules
Maximum PCB trace length for all signals	5000 mil
Spacing Rules for Address/Command/Control Signals
Minimum spacing between address/command/control signals	3 H², except: 1 H under adaptive SoC 1 H under DDR4 device
Minimum spacing between address/command/control and other signal types	5 H, except: 2 H under adaptive SoC 2 H under DDR4 device
Spacing Rules for Data Signals
Minimum spacing between data/DK/QK signals within the same byte	3 H, except: 1 H under adaptive SoC 1 H under DDR4 device
Minimum spacing between data/DK/QK signals between different bytes	5 H, except: 2 H under adaptive SoC 2 H under DDR4 device
Minimum spacing between data/DK/QK signals and other signal types	5 H, except: 2 H under adaptive SoC 2 H under DDR4 device
Routing Notes
x18 Devices
DQ[8:0], DK0, DK0_B, DM0, QK0, QK0_B	Must be routed on the same layer
DQ[17:9], DK1, DK1_B, DM1, QK1, QK1_B	Must be routed on the same layer
x36 Devices
DQ[8:0], DQ[26:18], DK0, DK0_B, DM0, QK0, QK0_B, QK2, QK2_B	Must be routed on the same layer
DQ[17:9], DQ[35:27], DK1, DK1_B, DM1, QK1, QK1_B, QK3, QK3_B	Must be routed on the same layer
Up to 60 Ω (single-ended) or 120 Ω (differential) under adaptive SoC or DRAM devices, taking into account PCB manufacturing tolerances. H is the distance to the nearest ground return plane.