The following table defines routing rules for QDR-IV signals.
| Parameter | Value |
|---|---|
| Impedance Rules | |
| Impedance for single-ended address/command/control and data signals | 50Ω 1 ± 10% |
| Differential impedance for clock (CK), data write clock (DK), and data read clock (QK) | 90Ω 1 ± 10% |
| Maximum Trace Length Rules | |
| Maximum PCB trace length for all signals | 5000 mil |
| Spacing Rules for Address/Command/Control Signals | |
| Minimum spacing between address/command/control signals |
3H 2 , except 1H under adaptive SoC or QDR-IV device |
| Minimum spacing between address/command/control signals and other signals |
5H 2 , except 2H under adaptive SoC or QDR-IV device |
| Spacing Rules for Data Signals | |
| Minimum spacing between data signals and DK/QK signals within the same byte |
3H 2 , except 1H under adaptive SoC or QDR-IV device |
| Minimum spacing between data signals and DK/QK signals between different bytes |
5H 2 , except 2H under adaptive SoC or QDR-IV device |
| Minimum spacing between data signals and DK/QK signals and other signals |
5H 2 , except 2H under adaptive SoC or QDR-IV device |
| Routing Notes for 2x18 (36-bit) Interfaces | |
| DQA[8:0], DKA0_P, DKA0_N, QKA0_P, QKA0_N, QVLDA[0] | Must be routed on the same routing layer |
| DQA[17:9], DKA1_P, DKA1_N, QKA1_P, QKA1_N, QVLDA[1] | Must be routed on the same routing layer |
| DQB[8:0], DKB0_P, DKB0_N, QKB0_P, QKB0_N, QVLDB[0] | Must be routed on the same routing layer |
| DQB[17:9], DKB1_P, DKB1_N, QKB1_P, QKA1_N, QVLDB[1] | Must be routed on the same routing layer |
| Routing Notes for 2x36 (72-bit) Interfaces | |
| DQA[17:0], DKA0_P, DKA0_N, QKA0_P, QKA0_N, QVLDA[0] | Must be routed on the same routing layer |
| DQA[35:18], DKA1_P, DKA1_N, QKA1_P, QKA1_N, QVLDA[1] | Must be routed on the same routing layer |
| DQB[17:0], DKB0_P, DKB0_N, QKB0_P, QKB0_N, QVLDB[0] | Must be routed on the same routing layer |
| DQB[35:18], DKB1_P, DKB1_N, QKB1_P, QKA1_N, QVLDB[1] | Must be routed on the same routing layer |
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