Physical Design Rules for LPDDR5 Signals

Physical Design Rules for LPDDR5 Signals - UG863

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID

UG863

Release Date

2025-03-04

Revision

1.9 English

The following table defines routing rules for LPDDR5 signals.

Table 1. Physical Design Rules for LPDDR5 Signals
Parameter	Value
Impedance Rules
Impedance for single-ended CAC¹ and data signals	40Ω ±10%
Impedance for differential clock, data clock and read data strobe signals	75Ω ±10%
PCB Trace Length Rules (from Adaptive SoC to Furthest Device or Termination)
Maximum PCB trace length for CAC/CK signals	2000 mil
Total Trace Length Rules (PCB + Adaptive SoC Package Routing to Furthest Device)
Maximum PCB trace length for data signals	2000 mil
Spacing Rules for CAC and Clock Signals
Minimum spacing between CAC signals within the same channel²	2.5H³, except: 1H under adaptive SoC or LPDDR5 device
Minimum spacing between CA signals and clock signals within the same channel²	5H³, except: 2H under adaptive SoC or LPDDR5 device
Minimum spacing between CAC/clock signals and data/strobe signals within the same channel²	7H³, except: 2H under adaptive SoC or LPDDR5 device
Spacing Rules for Data, Data Clock, and Read Data Strobe Signals
Minimum spacing between data signals within the same byte	2.5H³, except: 1H under adaptive SoC or LPDDR5 Device
Minimum spacing between data signals and WCK/RDQS signals within the same byte	5H³, except: 1H under adaptive SoC or LPDDR5 device
Minimum spacing between data signals and WCK/RDQS signals between different bytes	7H³, except: 2H under adaptive SoC or LPDDR5 device
Minimum spacing between data/WCK/RDQS signals and other signals within the same channel²	7H³, except: 2H under adaptive SoC or LPDDR5 device
Spacing Rules for Signals between Channels or Memory Interfaces
Minimum spacing between signals in one memory interface to signals in another channel or memory interface	7H³, except: 2H under adaptive SoC or LPDDR5 device
Maximum Vias per Signal
Data, WCK, and RDQS signals	2 each
Other Physical Design Requirements
Route all data/strobe signals within a byte on one internal signal layer
Place FPGA and LPDDR5 devices on the top side and route all data/strobe signals on upper internal layers
Maintain 2:1 signal to GND via ratio on the adaptive SoC side of the PCB
CAC stands for command/address/control. A channel is defined as either the “A” side of the LPDDR5 device or the “B” side of the LPDDR5 device. H is the distance to the nearest ground return plane. For single-rank LPDDR5, AMD recommends the use of blind vias or back-drilled vias. For dual-rank LPDDR5, AMD requires the use of blind vias or back-drilled vias.