Physical Design Rules for DDR5 Signals

Physical Design Rules for DDR5 Signals - UG863

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID

UG863

Release Date

2025-05-21

Revision

1.10 English

The following table defines routing rules for DDR5 signals.

Table 1. Physical Design Rules for DDR5 Signals
Parameter	Value
Impedance Rules
Impedance for single-ended CAC¹ and data signals	40Ω² ± 10%
Impedance for differential clock (CK) and data strobe (DQS)	75Ω² ± 10%
PCB Trace Length Rules (from Adaptive SoC to Furthest Device/DIMM Connector)
Maximum PCB trace length for CAC signals	10,000 mils
Maximum PCB trace length for data/strobe signals	5,000 mils (component interfaces) 4,000 mils (DIMM interfaces)
Spacing Rules for CAC Signals
Minimum spacing between CAC Signals	2H³, except: 1H under adaptive SoC 1.5H under DDR5 device
Minimum spacing between CAC signals and other signals	5H, except: 2H under adaptive SoC 2H under DDR5 device
Spacing Rules for Data and Data Strobe Signals
Minimum spacing between data/strobe signals within the same byte	2.5H, except: 1H under adaptive SoC 1.5H under DDR5 device
Minimum spacing between data/strobe signals to data/strobe signals in other bytes	5H, except: 2H under adaptive SoC 2H under DDR5 device
Minimum spacing between data/strobe signals to other signals	5H, except: 2H under adaptive SoC 2H under DDR5 device
Spacing Rules for Signals between Memory Interfaces
Minimum spacing between signals in one memory interface to signals in another memory interface	5H, except: 2H under adaptive SoC 2H under DDR5 device
Maximum Via Count per Signal Type
CAC signals and clock signals	(2 x # of devices) + 2
Data and strobe signals	2
Other Physical Design Requirements
Do not route CAC/clock signals on more than two internal signal layers
Do not route data/strobe signals on more than one internal signal layer
Route data/strobe signals on internal layers as close to the memory devices as possible
CAC stands for command/address/control. Up to 60Ω (single-ended) or 120Ω (differential) under adaptive SoC or DRAM devices, taking into account PCB manufacturing tolerances. H is the distance to the nearest ground return plane. AMD recommends the use of blind vias or back-drilled vias.