Physical Design Rules for DDR4 Signals - Physical Design Rules for DDR4 Signals

Physical Design Rules for DDR4 Signals - Physical Design Rules for DDR4 Signals - UG863

Versal Adaptive SoC PCB Design User Guide (UG863)

Document ID

UG863

Release Date

2026-02-20

Revision

1.11 English

The following table defines routing rules for DDR4 signals.

Table 1. Physical Design Rules for DDR4 Signals
Parameter	Value
Impedance Rules
Impedance for single-ended CAC¹ and data signals	50 Ω² ± 10%
Impedance for differential clock (CK) and data strobe (DQS)	90 Ω² ± 10%
Trace Length Rules (from Adaptive SoC to Furthest Device/Termination/DIMM Connector)
Maximum PCB trace length for CAC signals	11000 mils
Maximum PCB trace length for data/strobe signals	5500 mils
Spacing Rules for CAC Signals
Minimum spacing between CAC signals	2 H³, except: 1 H under adaptive SoC 1.5 H under DDR4 device
Minimum spacing between CAC signals and clock signals	5 H, except: 2 H under adaptive SoC 2 H under DDR4 device
Minimum spacing between CAC signals and data signals	5 H, except: 2 H under adaptive SoC 2 H under DDR4 device
Spacing Rules for Data and Data Strobe Signals
Minimum spacing between data/strobe signals within the same byte	2 H, except: 1 H under adaptive SoC 1.5 H under DDR4 device
Minimum spacing between data/strobe signals to data/strobe signals in other bytes	5 H, except: 2 H under adaptive SoC 2 H under DDR4 device
Spacing Rules for Signals between Memory Interfaces
Minimum spacing between signals in one memory interface to signals in another memory interface	5 H, except: 2 H under adaptive SoC 2 H under DDR4 device
Maximum Via Count per Signal Type
CAC signals and clock signals	(2 × # of devices) + 2
Data and strobe signals	2
Other Physical Design Requirements
Do not route CAC/clock signals on more than two internal signal layers
Do not route data/strobe signals for a data byte on more than one internal signal layer
Route data/strobe signals on internal layers as close to the memory devices as possible
CAC stands for command/address/control. Up to 60 Ω (single-ended) or 120 Ω (differential) under adaptive SoC or DRAM devices, taking into account PCB manufacturing tolerances. H is the distance to the nearest ground return plane. Refer to Required Memory Routing Guidelines for All Interfaces for more details.