This section provides PCB design guidelines for LPDDR5/5x interfaces.
Connections between the adaptive SoC and LPDDR5/5x device are defined along with
physical design rules and timing constraints.
Important: Follow
all routing guidelines in this section to achieve the maximum data rates
specified in the Versal adaptive SoC data sheets. You can have unique or specific
designs with particular violations of some rules. In these scenarios, make
design or routing trade-offs in other routing parameters to mitigate the risk.
System-level channel signal integrity simulations are required to evaluate such
trade-offs. It is important to read Required Memory Routing Guidelines for All Interfaces before continuing with this section.
Important: LPDDR5x devices can be
used in place of LPDDR5 devices but should only be operated at the LPDDR5 data
rates as specified in the Versal adaptive SoC data
sheets.