MIPI M-PHY/UFS - MIPI M-PHY/UFS - UG863

MIPI M-PHY/UFS is intended for flash memory storage and other high-bandwidth applications. This standard is supported in the dedicated MIPI M-PHY bank 507 in Versal AI Edge Series Gen 2.

• MIPI M-PHY/UFS PCB guidelines for impedance, trace length, spacing, and skew are shown below.
• Trace impedance of 100 Ω differential (±10%) is required for all pairs.
• PCB insertion loss should be < 6 dB at the Nyquist frequency with no large insertion loss variations (±2 dB) in the Nyquist frequency range.
• Crosstalk should be minimized up to the Nyquist frequency, with accumulated total < –30 dB with all aggressors in phase.
• Trace lengths for all differential signals should match to < 0.250 mm between P/M.
• Ensure solid ground return planes above and below routing layers.
• Signals should be routed with a maximum of two vias per trace.
• Place at least one ground stitch via near each signal via.
• TX and RX pairs should not be routed side-by-side in the same signal layer.
  • If this is done, the spacing should be > 6X PCB dielectric height, or meet the –30 dB crosstalk requirement.
• Use back-drill vias on TXD and RXD traces.
• Tie RESREF to ground via a 200 Ω resistor:
  • Specifications can be found in Versal AI Edge Series Gen 2 Data Sheet: DC and AC Switching Characteristics (DS1021).
• All clocks (PHY, UFS device, and MIO) can be generated from the same source.
• Reference clock (REF_PAD, bank 507) jitter and phase noise requirements can be found in Versal AI Edge Series Gen 2 Data Sheet: DC and AC Switching Characteristics (DS1021).
• The PHY reference clock (REF_PAD_CLK, bank 507) is recommended to be driven by a differential HCSL or LP-HCSL clock source. An LVDS oscillator can also be used if biased properly. The following are three examples showing HCSL, LP-HCSL, and LVDS, respectively.
  Figure 1. HCSL Schematic Termination
  Figure 2. LP-HCSL Schematic Termination
  Figure 3. LVDS Schematic Termination
• Other clock source standards can be used but must adhere to the voltage and swing requirements listed in the following table.

  Table 1. Clock Source Voltage and Swing Requirements

  Parameter	Min	Max
  Maximum input voltage level		0.88V
  Minimum voltage at pin	–0.15V
  Absolute maximum voltage at pin including overshoot		1.15V (10% of period)
  Absolute minimum voltage at pin including overshoot	–0.3V (10% of period)
  Single-ended input swing (VPP)	0.3V	0.88V
  Differential input swing (VPPDIFF)	0.3V	1.76V

• The configuration clock drives into the PS MIO interface and can be provided by a single-ended LVCMOS clock. Add series termination of 33 Ω as shown in the following figure.
  Figure 4. LVCMOS Clock Schematic Termination
• The UFS device clock can be provided by a single-ended LVCMOS clock. A level shifter might be required depending on the oscillator being used. Add series termination of 33 Ω as shown in the previous figure. Full clock specifications can be found in JEDEC specification JESD220E.