MIPI D-PHY - MIPI D-PHY - UG863

Versal Adaptive SoC PCB Design User Guide (UG863)
Document ID
UG863
Release Date
2026-02-20
Revision
1.11 English

MIPI D-PHY is intended for use in mobile devices including cameras, displays, and unified protocol interfaces. Support for this standard in Versal devices is in adherence to the MIPI alliance interface specifications. Typical MIPI D-PHY cores consist of four differential data lanes and one differential clock lane, as shown in the following figure.

Figure 1. MIPI D-PHY Transmitter and Receiver Paths

MIPI D-PHY PCB guidelines for impedance, channel requirements, spacing, skew, and termination are shown in the previous figure.

Table 1. MIPI D-PHY PCB Trace and Skew Guidelines
Parameter Specification
Trace type Stripline
Differential impedance 100±10% Ω
Channel requirement D-PHY insertion loss specification 1
Spacing in pair 2.5X trace width
Spacing to other MIPI pairs 5X trace width
Spacing to other non-MIPI pairs 6X trace width
Skew between P/N per pair ±2 ps 2
Skew between clock and data ±8 ps 2
Skew between data and data ±8 ps 2
Termination at receiver 100 Ω differential 3
  1. Channels are categorized into short/standard reach based on the DPHY insertion loss specification. For achievable system-level performance with specific channel at required speed, refer to the Operating Modes: Data Rate and Channel Support Guidance section in the MIPI D-PHY Specification (https://www.mipi.org/specifications/d-phy) and AMD device D-PHY signal integrity recommendation to decide if equalization should be enabled as well as the proper equalization setting for the transmitter and receiver.
  2. Include adaptive SoC package delays for all skew calculations.
  3. When adaptive SoC/FPGA/MPSoC is the receiver, 100 Ω on-chip termination is required via the DIFF_TERM attribute. Refer to the MIPI_DPHY section in Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).