MIPI D-PHY - UG863

Versal Adaptive SoC PCB Design User Guide (UG863)
Document ID
UG863
Release Date
2025-03-04
Revision
1.9 English

MIPI D-PHY is intended for use in mobile devices including cameras, displays, and unified protocol interfaces. Support for this standard in Versal devices is in adherence to the MIPI alliance interface specifications. Typical MIPI D-PHY cores consist of four differential data lanes and one differential clock lane, as shown in the following figure.

Figure 1. MIPI D-PHY Transmitter and Receiver Paths

MIPI D-PHY PCB guidelines for impedance, trace length, spacing, skew, and termination are shown in the previous figure.

Table 1. MIPI D-PHY PCB Trace and Skew Guidelines
Parameter Specification
Trace type Stripline
Differential impedance 95±10% Ω
Trace length ≤ 10.0 inches 1,2
Spacing in pair 2X trace width
Spacing to other MIPI pairs 5X trace width
Spacing to other non-MIPI pairs 6X trace width
Skew between P/N per pair ±2 ps
Skew between clock and data ±8 ps
Skew between data and data ±8 ps
Termination at receiver 100 Ω differential 3
  1. For distances greater than 4 inches, receiver equalization must be used (CTLE). It is strongly recommended that the PCB (data-to-data and data-to-clock) be deskewed even if the deskew feature in the IP is used.
  2. A reference stackup used for the longer trace lengths (4 to 10 inches) can be provided upon request. Operation at 2.5 Gb/s is supported as long as the channel loss is kept under 9 dB.
  3. When adaptive SoC/FPGA/MPSoC is the receiver, 100 Ω on-chip termination is recommended via the DIFF_TERM attribute. See the MIPI_DPHY section in Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).