MIPI C-PHY is intended for use in mobile and embedded devices including cameras, displays, and unified protocol interfaces supporting MIPI DSI-2 and CSI-2. This standard is supported in the X5IO banks of the Versal adaptive SoCs. Support for this standard in Versal devices is in adherence to the MIPI alliance interface specifications.
MIPI C-PHY cores consist of one or more three-wire lanes, as shown in the following figure. MIPI C-PHY lanes have embedded clocking, and no separate clock channels are required.
Figure 1. MIPI C-PHY Transmitter and Receiver Paths
MIPI C-PHY PCB guidelines for impedance, trace length, spacing, skew, and termination are shown in the following table.
| Parameter | Specification |
|---|---|
| Trace type | Stripline |
| Differential impedance between all pairs in trio A-B, B-C, and A-C | 100 Ω ± 10% |
| Single ended impedance | 50 Ω + 10% |
| Trace length | ≤ 10.0 inches |
| Spacing in trio | 2X trace width |
| Spacing to other MIPI C-PHY trio | 5X trace width |
| Spacing to other non-MIPI C-PHY signals | 6X trace width |
| Skew between lines in lane trio | ±2 ps |
| Skew between lanes | 160 ps |
| Termination at receiver | 50 Ω single-ended |