Host Sideband Signals (HSA, HSCL, HSDA)
HSA (I2C/I3C-Basic Host Sideband Bus Address)
Connect the appropriate value resistor to ground for the desired host identifier (HID) (see JESD300-5B.01). Each physical DIMM in the design must have a unique HSA value that matches the HID value selected in the DDRMC5 GUI. Refer to Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456) for more details.
| HAS Pin Connection | 3-bit HID | Comment |
|---|---|---|
| 10.0 kΩ to GND | HID = 000 | 1% resistor |
| 15.4 kΩ to GND | HID = 001 | |
| 23.2 kΩ to GND | HID = 010 | |
| 35.7 kΩ to GND | HID = 011 | |
| 54.9 kΩ to GND | HID = 100 | |
| 84.5 kΩ to GND | HID = 101 | |
| 127 kΩ to GND | HID = 110 | |
| 196 kΩ to GND | HID = 111 | |
| Tied directly to GND | HID = 000 | Offline mode; write protect override enabled |
HSCL and HSDA
HSCL and HSDA are used to strobe data into the HUB device on the DIMM and can operate at 1.0V or 1.8V. To ensure I3C compatibility, ensure that the HSDA and HSCL signals operate at 1.0V. Operating at 1.8V only permits I2C operation. A level shifter might be required to step down the HSDA/HSCL voltage level to 1.8V or 1.0V. If so, attach 2.2 kΩ pull-up resistors on HSCL and HSDA at the RDIMM side of the level shifter. Refer to JESD300-5B.01, JESD403-1C.01, and Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456).
RDIMM Signals
PCAMP (CAMP/PWR_GOOD) Pin
The CAMP/PCAMP pin defaults to PWR_GOOD functionality in adaptive SoC applications. This signal is not monitored by the adaptive SoC but PWR_GOOD must be asserted before releasing POR to ensure proper power sequencing. For additional electrical and functional requirements, refer to the server PMIC standards JESD301-1, JESD301-3, JESD301-4, and JESD301-5.
UDIMM Signals
PWR_EN and PWR_GOOD
The PWR_EN signal is directly connected to the VR_EN input of the DIMM PMIC, and it must be asserted High during power up to enable the PMIC. Per client PMIC standards (JESD301-2 and JESD301-6), the required input High level for this signal is 1.26 V to 3.6 V. As part of the power-up sequence:
- PWR_EN must be asserted High to initiate PCM operation.
- The system must wait for the PMIC to assert PWR_GOOD before releasing POR.
The PWR_GOOD signal is not monitored by the adaptive SoC. Therefore proper sequencing must be ensured externally.