XP5PHY_LS Ports - XP5PHY_LS Ports - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English
Table 1. XP5PHY_LS Ports
Port I/O Synchronous Clock Domain Description
CE[5:0] Input CTRL_CLK Clock Enable for the delay line. When enabled, the delay line increments (INC = 1) or decrements (INC = 0) a given BITSLICE's delay line by one delay tap. When updating an input or output delay in BITSLICE[x] through the RIU, CE must be set to 0.
CFGTRL_OUT[88:0] Output   Dedicated XP5IO PHY connection.
CNTVALUEIN[53:0] Input CTRL_CLK The delay value (in taps) to be loaded to the input or output delay selected by RXTX_SEL. Each BITSLICE is associated with nine bits of CNTVALUEIN. BITSLICE[0] is associated with CNTVALUEIN[8:0], BITSLICE[1] with CNTVALUEIN[17:9], BITSLICE[2] with CNTVALUEIN[26:18], BITSLICE[3] with CNTVALUEIN[35:27], BITSLICE[4] with CNTVALUEIN[44:36], and BITSLICE[5] with CNTVALUEIN[53:45].
CNTVALUEOUT[53:0] Output CTRL_CLK The delay value (in taps) of the input or output delay selected by RXTX_SEL. Each BITSLICE is associated with nine bits of CNTVALUEOUT. BITSLICE[0] is associated with CNTVALUEOUT[8:0], BITSLICE[1] with CNTVALUEOUT[17:9], BITSLICE[2] with CNTVALUEOUT[26:18], BITSLICE[3] with CNTVALUEOUT[35:27], BITSLICE[4] with CNTVALUEOUT[44:36], and BITSLICE[5] with CNTVALUEOUT[53:45].
CTRL_CLK Input   Clock used for RIU access, delay line updates, and BISC. CTRL_CLK must be driven by a free-running clock. The ratio of different CTRL_CLK frequencies of all nibbles in a bank cannot be greater than 4:1.

D0[7:0]

D1[7:0]

D2[7:0]

D3[7:0]

D4[7:0]

D5[7:0]

 Input DIV2/DIV4 internal XP5IO PHY clock derived from PLL_CLK TX data from the programmable logic for a given BITSLICE. For example, D0 controls BITSLICE[0] with the serialized data appearing on D0[0].
DFX_UNEXPECTED_ACTIVATION Output   Dedicated XP5IO PHY connection.
DLY_RDY Output CTRL_CLK Indicates that delay lines (input, output, quarter (PQTR/NQTR), and coarse (CRSE)) can now be changed. If using BISC, it also indicates that the alignment and delay calibration steps are completed. If multiple nibbles comprise an interface, the assertion time for DLY_RDY can vary for each nibble. Within simulation, the assertion time of DLY_RDY does not vary for each nibble in an interface, but varies as the XP5IO PHY configuration and connections change.
DMC_DIV4_CLK Output   Reserved for memory controller.
DYN_DCI[5:0] Output   DYN_DCI controls turning off/on receiver termination for BITSLICE[x]. DYN_DCI can only be used with buffers that have the DCITERMDISABLE port. See Controlling IBUF_DISABLE and DYN_DCI for more information.
EN_VTC Input CTRL_CLK Assert to enable VTC for a nibble. If asserted without RX_EN_VTC/TX_EN_VTC, only QTR delays undergo VTC.
FIFO_EMPTY Output

FIFO_RD_CLK (FIFO_MODE = ASYNC | SYNC)

Not applicable (FIFO_MODE = BYPASS)

 FIFO empty flag for this bit. When the FIFO write pointer and read pointer are the same, this signal is High. When inverted and registered, connect FIFO_EMPTY to FIFO_RD_EN to obtain a continuous data stream from the FIFO.
FIFO_RD_CLK Input   The deserialized received data is read from the FIFO using the FIFO_RD_CLK signal. The FIFO read clock can be generated by PLL/MMCM or come from the FIFO_WRCLK_OUT output.
FIFO_RDEN Input

FIFO_RD_CLK (FIFO_MODE = ASYNC | SYNC)

Not applicable (FIFO_MODE = BYPASS)

 Enables a read operation from the RX FIFO, active-High. When this signal is Low, the FIFO read pointer is held at the same position. The effect of this is that the Q output shows new data every eight clock cycles.
FIFO_WR_CLK Output   The FIFO write clock. For source-synchronous receive interfaces with DQS_SRC = LOCAL, this is generated internally from DATAIN[0] or inter-nibble clocking. If DQS_SRC = EXTERN, FIFO_WR_CLK is generated internally from inter-byte clocking. If using serial mode, FIFO_WR_CLK is generated internally from the PLL_CLK input.
GATE_DLY_OUT[13:0] Output   Dedicated XP5IO PHY connection.
GT_STATUS Output   Reserved for memory applications.
HCG_RXCTRL_IN[4:0] Input   Dedicated XP5IO PHY connection.
HCG_TXCTRL_IN[5:0] Input   Dedicated XP5IO PHY connection.
HCT_GT_STATUS_IN[6:0] Input   Dedicated XP5IO PHY connection.
HCT_MON_IN[3:0] Input   Dedicated XP5IO PHY connection.
HCT_REFCLKEN_IN Input   Dedicated XP5IO PHY connection.
HRT_PNSEL_IN[6:0] Input   Dedicated XP5IO PHY connection.
IBUF_DISABLE[5:0] Output   Disables the input buffer to reduce power.
IDLY0_OUT[13:0] Output   Dedicated XP5IO PHY connection.
IDLY1_OUT[13:0] Output   Dedicated XP5IO PHY connection.
IDLY2_OUT[13:0] Output   Dedicated XP5IO PHY connection.
IDLY3_OUT[13:0] Output   Dedicated XP5IO PHY connection.
IDLY4_OUT[13:0] Output   Dedicated XP5IO PHY connection.
IDLY5_OUT[13:0] Output   Dedicated XP5IO PHY connection.
INC[5:0] Input   Used with CE, LD, and CNTVALUEIN to change delay values on a per-BITSLICE basis. When updating an input or output delay in BITSLICE[x] through the RIU, INC is a don't care.
IOB2COMP_LSPEED_I[5:0] Input   Dedicated XP5IO PHY connection.
LCG_CTRL_OUT[18:0] Output   Dedicated XP5IO PHY connection.
LCT_CTRL_OUT[44:0] Output   Dedicated XP5IO PHY connection.
LCT_GT_CTRL_OUT[16:0] Output   Dedicated XP5IO PHY connection.
LD[5:0] Input CTRL_CLK Used with CE, INC, and CNTVALUEIN to change delay values on a per-BITSLICE basis. When updating an input or output delay in BITSLICE[x] through the RIU, LD must be set to 1.
LS_HS_FIXDLY_RDY Output   Dedicated XP5IO PHY connection.
LS_HS_LSHS_LP_TX_O_OR_PU_EN_0[2:0] Output   Dedicated XP5IO PHY connection.
LS_HS_LSHS_LP_TX_O_OR_PU_EN_1[2:0] Output   Dedicated XP5IO PHY connection.
LS_HS_LSHS_LP_TX_T_OR_PD_EN_0[2:0] Output   Dedicated XP5IO PHY connection.
LS_HS_PHY_RDY Output   Dedicated XP5IO PHY connection.
LS_HS_PRIME_VAL Output   Dedicated XP5IO PHY connection.
MIN_DLY_OUT[15:0] Output   Dedicated XP5IO PHY connection.
NQTR_DLY_OUT[14:0] Output   Dedicated XP5IO PHY connection.
ODLY0_OUT[14:0] Output   Dedicated XP5IO PHY connection.
ODLY1_OUT[14:0] Output   Dedicated XP5IO PHY connection.
ODLY2_OUT[14:0] Output   Dedicated XP5IO PHY connection.
ODLY3_OUT[14:0] Output   Dedicated XP5IO PHY connection.
ODLY4_OUT[14:0] Output   Dedicated XP5IO PHY connection.
ODLY5_OUT[14:0] Output   Dedicated XP5IO PHY connection.
PHY_RDEN[3:0] Input Internal XP5IO PHY clock derived from PLL_CLK Read enable. Must be tied to 1111 when the RX_GATING attribute is not used.
PHY_RDY Output   Indicates that the XPHY is ready for VTC. EN_VTC must be asserted for the first PHY_RDY assertion. Afterwards, if EN_VTC is deasserted, PHY_RDY stays asserted. If EN_VTC is then reasserted, PHY_RDY deasserts and then reasserts.
PHY_WREN[3:0] Input Internal XP5IO PHY clock derived from PLL_CLK When TBYTE_CTL_x is set to PHY_WREN, the PHY_WREN input is inverted and serialized before being used as the tristate control signal (T_OUT[x]) for BITSLICE[x]. The inverted and serialized PHY_WREN is output on T_OUT synchronously with the TX data. Unlike T, which has each of its bits mapped to a BITSLICE, PHY_WREN is applied to each BITSLICE in a nibble. Each bit of PHY_WREN controls the tristate enable of two UIs worth of data. PHY_WREN is not supported when TX_DATA_WIDTH = 2.

PHY_WREN must be deasserted during the reset sequence and when issuing a BS_RESET from the RIU interface.

  • If TX_DATA_WIDTH = 8: [3:0]
  • If TX_DATA_WIDTH = 4: [2][0]
  • If TX_DATA_WIDTH = 2: not supported
PHY2PHY_BISC_START_IN Input   For simulation purposes.
PHY2PHY_BISC_START_OUT Output   For simulation purposes.
PHY2PHY_BISC_STOP_IN Input   For simulation purposes.
PHY2PHY_BISC_STOP_OUT Output   For simulation purposes.
PQTR_DLY_OUT[14:0] Output   Dedicated XP5IO PHY connection.

Q0[7:0]

Q1[7:0]

Q2[7:0]

Q3[7:0]

Q4[7:0]

Q5[7:0]

 Output

FIFO_RD_CLK (FIFO_MODE = ASYNC | SYNC)

FIFO_WR_CLK (FIFO_MODE = BYPASS)

 Deserialized RX data from the FIFO or from bypassing the FIFO for a given BITSLICE. For example, Q0 is the word created from DATAIN[0].
RIU_ADDR[7:0] Input CTRL_CLK The address input bus provides a register address for the register interface. The address value on this bus specifies the configuration and status bits that are written or read with the next CTRL_CLK cycle. When not used, all bits must be assigned zeros.
RIU_CTRL_OUT[42:0] Output   Dedicated XP5IO PHY connection.
RIU_NIBBLE_SEL Input CTRL_CLK Assert High to perform read/write operations on the RIU for a given nibble.
RIU_RD_DATA[15:0] Output CTRL_CLK This output bus provides RIU data to the internal logic. The value of this bus is a representation of the register bits addressed by RIU_ADDR. The data is presented in the next cycle when RIU_WR_EN is Low and RIU_NIBBLE_SEL is High, sampled by RIU.
RIU_RD_VALID Output CTRL_CLK RIU_RD_VALID indicates the status when RIU accesses are made from interconnect logic while the internal BISC state machines are also accessing the RIU registers. RIU writes by BISC take precedence over RIU writes from the PL. If an RIU write from the PL collides with one from BISC, RIU_RD_VALID deasserts and the PL RIU write from the cycle before RIU_RD_VALID deasserted is stored. After BISC finishes its write(s), RIU_RD_VALID asserts and the stored PL RIU write is executed. Any writes from the PL while RIU_RD_VALID is Low are discarded. In addition to collisions, the RIU_VALID asserts when writing to the RL_DLY_RNK[0, 1, 2, 3] registers. These registers are unique because it takes more than two cycles for an RIU write to update them. Therefore, back-to-back accesses to these registers are impossible.
RIU_WR_DATA[15:0] Input CTRL_CLK RIU data to be written into RIU interface when enabled. The data is presented in the cycle that RIU_WR_EN and RIU_NIBBLE_SEL are active. The data is captured in a shadow register and written at a later time. RIU_VALID indicates when the RIU port is ready to accept another write.
RIU_WR_EN Input CTRL_CLK Assert High to enable writes to the RIU. RIU writes also require that RIU_RD_VALID is HIGH.
RST Input   Resets the entire XPHY nibble, including all RX datapaths, TX datapaths, and delays. While RST is asserted, all TX IOBs and the tristate control signal are set to the values of TX_INIT_# and TX_INIT_TRI, respectively.
RX_EN_VTC[5:0] Input CTRL_CLK Assert to enable the Alignment and Delay Calibration steps of BISC to be performed on the input delays. If EN_VTC is also asserted, VTC is performed on the input delays. When updating an input or output delay in BITSLICE[x] through the PL, both RX_EN_VTC[x] and TX_EN_VTC[x] must be set to 0. However, when updating an input or output delay in BITSLICE[x] through the RIU, both RX_EN_VTC[x] and TX_EN_VTC[x] must be set to 1.
RX_RST[5:0] Input   Assert to reset RX datapaths on a per-BITSLICE basis. Does not reset the input delay.

RXD0_IN[6:0]

RXD1_IN[6:0]

RXD2_IN[6:0]

RXD3_IN[6:0]

RXD4_IN[6:0]

RXD5_IN[6:0]

 Input   XP5PHY_HS to XP5PHY_LS dedicated connection.
RXTX_SEL[5:0] Input CTRL_CLK When 0, RXTX_SEL applies CE, INC, LD, and CNTVALUEIN to the input delay. Similarly, the input delay value is reported by CNTVALUEOUT. When 1, RXTX_SEL applies CE, INC, LD, and CNTVALUEIN to the output delay. Similarly, the output delay value is reported by CNTVALUEOUT.
T[5:0] Input   When TBYTE_CTL_x = T, T[x] is used as the tristate control signal. T is a combinatorial route and is not synchronized to the TX data.
TRID_OUT[4:0] Output   XP5PHY_HS to XP5PHY_LS dedicated connection.
TSTATE_DLY_OUT[13:0] Output   XP5PHY_HS to XP5PHY_LS dedicated connection.
TX_EN_VTC[5:0] Input CTRL_CLK Assert to enable the alignment and delay calibration steps of BISC to be performed on the input delays. If EN_VTC is also asserted, VTC is performed on the input delays. When updating an input or output delay in BITSLICE[x] through the PL, both RX_EN_VTC[x] and TX_EN_VTC[x] must be set to 0. However, when updating an input or output delay in BITSLICE[x] through the RIU, both RX_EN_VTC[x] and TX_EN_VTC[x] must be set to 1.
TX_RST[5:0] Input   Assert to reset TX datapaths on a per-BITSLICE basis. Does not reset the output delay. While TX_RST[x] is asserted, the TX IOB of BITSLICE[x] and the tristate control signal are set to the values of TX_INIT_x and TX_INIT_TRI, respectively.
TXD0_OUT[11:0] Output   XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD1_OUT[11:0] Output   XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD2_OUT[11:0] Output   XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD3_OUT[11:0] Output   XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD4_OUT[11:0] Output   XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD5_OUT[11:0] Output   XP5PHY_HS to XP5PHY_LS dedicated connection.