XP5PHY_LS Attributes - XP5PHY_LS Attributes

Table 1. XP5PHY_LS Attributes
Attribute	Values	Default	Type	Description
CASCADE_0 CASCADE_1 CASCADE_2 CASCADE_3 CASCADE_4 CASCADE_5	TRUE, FALSE	FALSE	Boolean	When TRUE enables the cascaded delay.
CONTINUOUS_DQS	TRUE, FALSE	FALSE	Boolean	Used with the RX_GATING attribute and the PHY_RDEN port to gate the capture clock entering on BITSLICE[0] or from inter-byte or inter-nibble clocking. The capture clock must be continuous (not a strobe) to set CONTINUOUS_DQS = TRUE. Because the capture clock is continuous and because there is no timing requirement between PHY_RDEN and the capture clock, the gate enable and disable is not cycle accurate to the capture clock (RX_GATING = ENABLE, CONTINUOUS_DQS = TRUE in this case). In contrast, when RX_GATING = ENABLE and CONTINUOUS_DQS = FALSE, gate enable and disable can be trained to be deterministic. Setting CONTINUOUS_DQS = TRUE requires that two capture clock cycles be received prior to receiving data to prevent data loss. See the description of PHY_RDEN in Table 1 for more information.
DELAY_VALUE_0 DELAY_VALUE_1 DELAY_VALUE_2 DELAY_VALUE_3 DELAY_VALUE_4 DELAY_VALUE_5	0–1250	0	Decimal	DELAY_VALUE_x is the delay in ps that is used for the input and output delays for the respective BITSLICE[x]. If CASCADE_x = TRUE, the maximum value of DELAY_VALUE_x extends from 625 ps to 1250 ps. For BITSLICEs with TX_OUTPUT_PHASE_90_x = TRUE, the DELAY_VALUE_x must be set to 0. For BITSLICEs in a nibble with RX_CLK_PHASE_<P\|N> = SHIFT_90, at least one of the BITSLICEs within the nibble must have DELAY_VALUE_x = 0. A non-zero delay requires SELF_CALIBRATE = ENABLE. For interfaces with PLL_CLK below 500 MHz, DELAY_VALUE is not supported. Consequently, delays need to be updated using the CNTVALUEIN, CE, INC, and LD ports.
DIS_IDLY_VT_TRACK	TRUE, FALSE	FALSE	Boolean	TRUE Disables VTC on input delays. FALSE Enables VTC on input delays.
DIS_ODLY_VT_TRACK	TRUE, FALSE	FALSE	Boolean	TRUE Disables VTC on output delays. FALSE Enables VTC on output delays.
DIS_QDLY_VT_TRACK	TRUE, FALSE	FALSE	Boolean	TRUE Disables VTC on QTR delays. FALSE Enables VTC on QTR delays.
DQS_MODE	DDR3, DDR4_1TCK, DDR4_2TCK, LPDDR4_TOGGLE, LPDDR4	DDR4_1TCK	String	Reserved for memory applications only.
DQS_SRC	EXTERN, LOCAL	LOCAL	String	LOCAL Set to LOCAL if the strobe is sourced from the connecting IOB, if its source and destination nibble are the same (the latter would require TXRX_LOOPBACK_x = TRUE for BITSLICE[x]), or if SERIAL_MODE = TRUE. EXTERN Set to EXTERN if the strobe enters through inter-byte clocking. DQS_SRC can be set to either value for nibbles receiving a strobe through inter-nibble clocking.
EN_CLK_TO_LOWER	ENABLE, DISABLE	DISABLE	String	ENABLE Enables inter-byte clocking to lower vertical location (see below). DISABLE Disables inter-byte clocking to lower vertical location. NIBBLE2 connects to NIBBLE4 NIBBLE3 connects to NIBBLE5 NIBBLE4 connects to NIBBLE6 NIBBLE5 connects to NIBBLE7 NIBBLE6 connects to NIBBLE8 NIBBLE7 connects to NIBBLE9
EN_CLK_TO_UPPER	ENABLE, DISABLE	DISABLE	String	ENABLE Enables inter-byte clocking to higher vertical location (see below). DISABLE Disables inter-byte clocking to higher vertical location. NIBBLE7 connects to NIBBLE10 NIBBLE6 connects to NIBBLE4 NIBBLE5 connects to NIBBLE3 NIBBLE4 connects to NIBBLE2 NIBBLE3 connects to NIBBLE1 NIBBLE2 connects to NIBBLE0
EN_DYN_DLY_MODE	TRUE, FALSE	FALSE	Boolean	Reserved for memory applications only.
EN_OTHER_NCLK	TRUE, FALSE	FALSE	Boolean	TRUE Enables sourcing the n-side of the strobe from inter-nibble clocking. FALSE Disables sourcing the n-side of the strobe from inter-nibble clocking.
EN_OTHER_PCLK	TRUE, FALSE	FALSE	Boolean	TRUE Enables sourcing the p-side of the strobe from inter-nibble clocking. FALSE Disables sourcing the p-side of the strobe from inter-nibble clocking.
FAST_CK	TRUE, FALSE	FALSE	Boolean	Reserved for memory applications only.
FIFO_MODE_0 FIFO_MODE_1 FIFO_MODE_2 FIFO_MODE_3 FIFO_MODE_4 FIFO_MODE_5	ASYNC, SYNC, BYPASS	ASYNC	String	ASYNC Set to ASYNC if the read and write clocks of the FIFO in BITSLICE[x] are the same frequency but phase independent. SYNC Set to SYNC if the read and write clocks of the FIFO in BITSLICE[x] are the same clock. SYNC requires a continuous receive data clock. BYPASS Set to BYPASS for the FIFO in BITSLICE[x] to forward the data to the fabric (it is not stored in the FIFO like in the ASYNC and SYNC settings). A zero cycle path is possible here. BYPASS requires a continuous receive data clock.
HISTO_EN	ENABLE, DISABLE	ENABLE	String	Reserved. Set to DISABLE.
HISTO_STEPSIZE	0–4095	4095	Decimal	Reserved.
HISTO_TH0	0–4095	819	Decimal	Reserved.
HISTO_TH1	0–4095	3276	Decimal	Reserved.
IBUF_DIS_SRC_0 IBUF_DIS_SRC_1 IBUF_DIS_SRC_2 IBUF_DIS_SRC_3 IBUF_DIS_SRC_4 IBUF_DIS_SRC_5		EXTERNAL		EXTERNAL IBUF_DISABLE is controlled by PL INTERNAL IBUF_DISABLE is controlled by XP5IO circuitry (PHY_RDEN, RD_IDLE_COUNT)
INV_RXCLK	TRUE, FALSE	FALSE	Boolean	Inverts the incoming strobe to BITSLICE[0].
LP4_DQS	TRUE, FALSE	FALSE	Boolean	Reserved for memory use only.
ODELAY_BYPASS_0 ODELAY_BYPASS_1 ODELAY_BYPASS_2 ODELAY_BYPASS_3 ODELAY_BYPASS_4 ODELAY_BYPASS_5	TRUE, FALSE	FALSE	Boolean	Reserved for memory use only.
ODT_SRC_0 ODT_SRC_1 ODT_SRC_2 ODT_SRC_3 ODT_SRC_4 ODT_SRC_5	INTERNAL, EXTERNAL	EXTERNAL	String	Controls DYN_DCI source: EXTERNAL DYN_DCI controlled by the PL INTERNAL DYN_DCI controlled by XP5IO PHY
REFCLK_FREQUENCY	200.0–4266.0	200	Floating	Set to the frequency of PLL_CLK.
RX_CLK_PHASE_N	SHIFT_0, SHIFT_90	SHIFT_0	String	SHIFT_0 Set to SHIFT_0 to not apply a phase shift to the n-clk. SHIFT_90 Set to SHIFT_90 to apply a positive 90° phase shift (relative to the data) to the n-clk. This phase shift is not retained for inter-nibble clocking. Setting RX_CLK_PHASE_N = SHIFT_90 requires that SELF_CALIBRATE = ENABLE. DELAY_VALUE_x of all BITSLICEs must be set to 0 in nibbles where RX_CLK_PHASE_N = SHIFT_90.
RX_CLK_PHASE_P	SHIFT_0, SHIFT_90	SHIFT_0	String	SHIFT_0 Set to SHIFT_0 to not apply a phase shift to the p-clk. SHIFT_90 Set to SHIFT_90 to apply a positive 90° phase shift (relative to the data) to the p-clk. This phase shift is not retained for inter-nibble clocking. Setting RX_CLK_PHASE_P = SHIFT_90 requires that SELF_CALIBRATE = ENABLE. DELAY_VALUE_x of all BITSLICEs must be set to 0 in nibbles where RX_CLK_PHASE_P = SHIFT_90.
RX_DATA_WIDTH	2, 4, 8	8	Decimal	Set 1:2, 1:4, or 1:8 deserialization.
RX_GATING	ENABLE, DISABLE	DISABLE	String	Used with the RX_DATA_WIDTH and CONTINUOUS_DQS attributes, as well as the PHY_RDEN port, to gate the strobe entering on BITSLICE[0] or from inter-byte or inter-nibble clocking. RX_GATING is necessary for bidirectional clocks which can be tristated when not active, or for strobes that are indeterministic on start-up or during normal operation. See the description of PHY_RDEN in Table 1 for more information.
SELF_CALIBRATE	ENABLE, DISABLE	ENABLE	String	ENABLE Enables BISC (proper assertion of EN_VTC, RX_EN_VTC, and TX_EN_VTC is still required) DISABLE Disables BISC.
SERIAL_MODE	TRUE, FALSE	FALSE	Boolean	TRUE Set to TRUE for interfaces where data is received without an accompanying source synchronous clock (strobe). In this case, the capture clock is generated internally from the PLL_CLK input. FALSE Set to FALSE for source-synchronous interfaces.
STOP_AFTER_ALIGN	TRUE, FALSE	FALSE	Boolean	Reserved.
TBYTE_CTL_0 TBYTE_CTL_1 TBYTE_CTL_2 TBYTE_CTL_3 TBYTE_CTL_4 TBYTE_CTL_5	T, PHY_WREN	T	String	T Set to T if using the T input (combinatorial path from the PL) as the tristate control signal for BITSLICE[x]. If TX_DATA_WIDTH = 2, only T (not PHY_WREN) can be used as the tristate control signal. PHY_WREN Set to PHY_WREN if using the PHY_WREN input as the tristate control signal for BITSLICE[x]. The serialized and inverted PHY_WREN is synchronized with the TX data. Each bit of PHY_WREN controls the tristate for two bits of data. T and PHY_WREN can both be applied to the same BITSLICE, and the BITSLICE selects which one to use based on its TBYTE_CTL_x setting.
TXRX_LOOPBACK_0 TXRX_LOOPBACK_1 TXRX_LOOPBACK_2 TXRX_LOOPBACK_3 TXRX_LOOPBACK_4 TXRX_LOOPBACK_5	TRUE, FALSE	FALSE	Boolean	TRUE Set to TRUE to loop back the TX output to RX input of the same BITSLICE[x]. The TX output still reaches the IOB. An I/O buffer must be used for loopback to work. Connect the net from XPHY.O0[x] to the input of an OBUF, IOBUF, or variant of one of the two. Alternatively, connect the output net from an IBUF, IOBUF, or a variant of one of the two to XPHY.DATAIN[x]. Only use one buffer (IBUF, OBUF, or variant) in this path. FALSE Set to FALSE for no loopback and for all unused BITSLICEs. TXRX_LOOPBACK_# is not supported when SERIAL_MODE = TRUE.
TX_DATA_WIDTH	2, 4, 8	8	Decimal	Set 2:1, 4:1, or 8:1 serialization. If TX_DATA_WIDTH = 2, any IOBs connected to the nibble cannot use PRE_EMPHASIS.
TX_GATING	ENABLE, DISABLE	DISABLE	String	DISABLE The TX datapath of BITSLICE[5,4,3,2,0] are not gated. ENABLE Use PHY_WREN to gate the TX datapath of BITSLICE[5,4,3,2,0]. BITSLICE[1] cannot be gated through this attribute, regardless of its setting.
TX_INIT_0 TX_INIT_1 TX_INIT_2 TX_INIT_3 TX_INIT_4 TX_INIT_5	1'b0, 1'b1	1'b0	Binary	1'b0 Sets the TX IOB value associated with BITSLICE[x] during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b0. 1'b1 Sets the TX IOB value associated with BITSLICE[x] during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b1.
TX_INIT_TRI	1'b0, 1'b1	1'b1	Binary	1'b0 Sets the tristate control signal during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b0. 1'b1 Sets the tristate control signal during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b1.
TX_OUTPUT_PHASE_90_0 TX_OUTPUT_PHASE_90_1 TX_OUTPUT_PHASE_90_2 TX_OUTPUT_PHASE_90_3 TX_OUTPUT_PHASE_90_4 TX_OUTPUT_PHASE_90_5	TRUE, FALSE	FALSE	Boolean	Used for TX signals to center align the transmit clock to data. Set to TRUE for clock and FALSE for data to achieve a center-aligned clock and data relationship. TRUE Applies a positive 90° phase shift to the TX output of BITSLICE[x]. DELAY_VALUE_x should be set to 0 when TX_OUTPUT_PHASE_90_x = TRUE. FALSE Set to FALSE to not apply the 90° shift.
TX_OUTPUT_PHASE_90_TRI	TRUE, FALSE	FALSE	Boolean	Used for center-aligned DDR TX signals where tristate control is required. Only applicable when TBYTE_CTL_x = PHY_WREN. Each BITSLICE being tristated must have its associated DELAY_VALUE_x set to 0. TRUE Applies a positive 90° phase shift to T_OUT[x]. FALSE FALSE: Does not apply the 90° phase shift.
WRITE_LEVELING	TRUE, FALSE	FALSE	Boolean	Reserved for memory applications only.

XP5PHY_LS Attributes - XP5PHY_LS Attributes - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)