XP5PHY_HS Ports - XP5PHY_HS Ports - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English
Table 1. X5PHY_HS Ports
Port I/O Description
CFGTRL_IN[88:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
CLB2PHY_CTRL_DLY_TEST_IN Input Dedicated PHY connection.
CLK_FROM_EXT Input Inter-byte clock input. Dedicated PHY connection.
CLK_TO_EXT_NORTH Output

Inter-byte clock output. Connects:

  • NIBBLE7 > NIBBLE10
  • NIBBLE6 > NIBBLE4
  • NIBBLE5 > NIBBLE3
  • NIBBLE4 > NIBBLE2
  • NIBBLE3 > NIBBLE1
  • NIBBLE2 > NIBBLE0

TO_EXT_NORTH for inter-byte clocking from XPHY nibble 6 to XPHY nibble 8. In being part of inter-byte clocking, CLK_TO_EXT_NORTH can only be connected to CLK_FROM_OTHER_XPHY of another nibble and cannot be connected to the programmable logic.
CLK_TO_EXT_SOUTH Output

Inter-byte clock output. Connects:

  • NIBBLE2 > NIBBLE4
  • NIBBLE3 > NIBBLE5
  • NIBBLE4 > NIBBLE6
  • NIBBLE5 > NIBBLE7
  • NIBBLE6 > NIBBLE8
  • NIBBLE7 > NIBBLE9

In being part of inter-byte clocking, CLK_TO_EXT_SOUTH can only be connected to CLK_FROM_OTHER_XPHY of another nibble and cannot be connected to the programmable logic.
FIXDLY_RDY Input XP5PHY_HS to XP5PHY_LS dedicated connection.
GATE_DLY_IN[13:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
HCG_RXCTRL_OUT[4:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
HCG_TXCTRL_OUT[5:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
HCT_GT_STATUS_OUT[6:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
HCT_MON_OUT[3:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
HCT_REFCLKEN_OUT Output XP5PHY_HS to XP5PHY_LS dedicated connection.
HRT_PHY2IOB_O0[5:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
HRT_PHY2IOB_T[5:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
HRT_PNSEL_OUT[6:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
IDLY0_IN[13:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
IDLY1_IN[13:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
IDLY2_IN[13:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
IDLY3_IN[13:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
IDLY4_IN[13:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
IDLY5_IN[13:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
IOB2PHY_RX_D[5:0] Input RX data from the IOB. DATAIN[0] enters NIBBLESLICE[0], DATAIN[1] enters NIBBLESLICE[1], and so on. The data is collected and stored in the FIFO of the corresponding NIBBLESLICE, after which it is output on the corresponding Q port (Q0 maps to NIBBLESLICE[0], and so on).
LCG_CTRL_IN[18:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
LCT_BSC_PHY_RDY Input XP5PHY_HS to XP5PHY_LS dedicated connection.
LCT_CTRL_IN[44:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
LCT_GT_CTRL_IN[16:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
MIN_DLY_IN[15:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
NDQS_GT_IN Input XP5PHY_HS to XP5PHY_LS dedicated connection.
NDQS_GT_OUT Output XP5PHY_HS to XP5PHY_LS dedicated connection.
NQTR_DLY_IN[14:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
ODLY0_IN[14:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
ODLY1_IN[14:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
ODLY2_IN[14:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
ODLY3_IN[14:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
ODLY4_IN[14:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
ODLY5_IN[14:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
PDQS_GT_IN Input Dedicated PHY connection between XP5PHY_HS nibble pairs.
PDQS_GT_OUT Output Dedicated PHY connection between XP5PHY_HS nibble pairs.
PLL_CLK Input Clocks the XP5IO PHY interface for TX, serial applications for RX, and for BISC calibration. Must be connected to CLKOUTPHY of an XPLL capable of routing to the nibble. If PLL_CLK is less than 500 MHz, DELAY_VALUE_<0-5> and VTC are not supported. Set the REFCLK_FREQUENCY attribute to the same value as the PLL_CLK frequency.
PQTR_DLY_IN[14:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
PRIME_VAL Input XP5PHY_HS to XP5PHY_LS dedicated connection.
RIU_CTRL_IN[42:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
RXD0_OUT[6:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
RXD1_OUT[6:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
RXD2_OUT[6:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
RXD3_OUT[6:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
RXD4_OUT[6:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
RXD5_OUT[6:0] Output XP5PHY_HS to XP5PHY_LS dedicated connection.
TRID_IN[4:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
TSTATE_DLY_IN[13:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD0_IN[11:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD1_IN[11:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD2_IN[11:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD3_IN[11:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD4_IN[11:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
TXD5_IN[11:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
XMC_IDELAY_FDLY[17:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.
XMC_ODELAY_FDLY[20:0] Input XP5PHY_HS to XP5PHY_LS dedicated connection.