XP5IO PHY Nibble - XP5IO PHY Nibble - UG861

The XP5IO PHY is the high-performance I/O interface for an XP5IO bank. Every XP5IO bank has eleven nibbles. Each nibble is defined as six NIBBLESLICEs and its associated features. NIBBLESLICEs contain input and output logic and are composed of a serializer, deserializer, I/O delays, and a receiver FIFO. NIBBLESLICEs can operate as a transmitter, receiver, or bidirectional circuit. A nibble also performs the following functions/features:

• Built-in self-calibration (BISC) aids in alignment and uses voltage and temperature compensation (VTC) to adjust delay lines
• Generates clocks for the receiver and transmitter functions in the NIBBLESLICEs
• Gives access to the register interface unit (RIU) that provides access to all features of a PHY nibble
• Tristate control
• TX to RX loopback
• Serial mode, which supports receiver interfaces where the clock and data phase relationship is unknown (any interface that is not source-synchronous)

The layout of nibbles in an XP5IO bank is represented in the following figure.

The following figure is a detailed view of the previous figure, representing the relationship between a single nibble XP5IO bank.

For source-synchronous receive applications (RX), the XP5IO PHY uses inter-byte clocking and inter-nibble clocking to route the source synchronous capture clock (strobe) to the different nibbles within a bank. Inter-byte clocking forwards the capture clock from one nibble to an adjacent byte group but routing is restricted. The following table shows how the capture clock is routed using inter-byte clocking.

After the capture clock is routed to a byte group, inter-nibble clocking routes the capture clock to either of the nibbles within the byte group. The byte groups are as follows:

• Byte group 0: NIBBLE0, NIBBLE1
• Byte group 1: NIBBLE2, NIBBLE3
• Byte group 2: NIBBLE4, NIBBLE5
• Byte group 3: NIBBLE6, NIBBLE7
• Byte group 4: NIBBLE8, NIBBLE9
• Byte group 5: NIBBLE10

Due to the routing restrictions of the inter-byte clocking, placement of the capture clock in a given nibble can restrict which nibbles can be used in a source-synchronous receive application. As shown in the following table, placing the capture clock in nibble 0 restricts the receiver application to nibbles 0 and 1. Moving the capture clock to nibble 5 allows the receiver application to be placed in any of the nibbles (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10).

The following figure shows a NIBBLESLICE.