XP5IO contains a PHY to support the high-performance I/O interfaces like LPDDR5 and MIPI D-PHY. There are eleven PHY nibbles in an XP5IO bank, with each PHY nibble containing six NIBBLESLICEs that transmit and/or receive data from six individual I/O pins, for a total of 66 pins per bank. Each NIBBLESLICE is composed of a serializer, deserializer, I/O delays, and receiver FIFO. The PHY is equipped with voltage and temperature compensation (VTC) and a mechanism for automatic delay adjustment for optimal data eye centering through the built-in self-calibration (BISC) feature in each PHY nibble. I/O delays can also be controlled through the programmable logic. Control of the PHY features is available through the register interface unit (RIU) in each nibble. The PHY system is composed of two parts. The XP5PHY_LS includes all interfaces that connect to the fabric logic while the XP5PHY_HS contains the primary high-speed logic resources of the PHY. When bypassing the PHY, designs might route connections through both the XP5PHY_HS and XP5PHY_LS to interface with the fabric logic, but no PHY resources can be enabled in this configuration.
The XP5IO PHY is used to support the following applications:
- LPDDR5 integrated memory controllers
- MIPI D-PHY v1.2
- General-purpose source synchronous and asynchronous PHY-based interfaces