VRP External Resistance Design Migration Guidelines - VRP External Resistance Design Migration Guidelines - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

In Spartan UltraScale+ devices, irrespective of the DCI termination value requirement, the external resistor on the VRP (HP I/O bank) or VR (XP5IO bank) pin is required to be 240 Ω. Instead of two resistors, only one resistor is required at an UltraScale+ device VRP or VR pin. With HP I/O banks the reference resistor is tied to ground, while in XP5IO banks, the reference resistor is tied to the bank VCCO in which the pin resides. For XP5IO banks, VR pins must be populated with a 240Ω reference resistor to the bank's VCCO, while in HP banks the VRP pin must tied to ground if the DCI functionality is used in the HP bank. The exact value of the split-termination or single-termination resistors are determined by the user-controllable ODT attribute.

Possible ODT values for split-termination DCI standards (HSTL and SSTL) are RTT_40, RTT_48, or RTT_60.

Important: The ODT value represents the desired Thevenin resistance to VCCO/2 for split-termination DCI standards.

Possible ODT values for single-termination POD standards are RTT_40, RTT_48, or RTT_60. Possible ODT values for single-termination HSUL standards are RTT_120, RTT_240, or RTT_NONE.

Important: The ODT value represents the desired resistance to VCCO for single-termination DCI standards.

The termination value for the controlled impedance driver is determined by the DCI state machine when a DCI standard with a controlled impedance driver is chosen, using OUTPUT_IMPEDANCE attribute values. Possible values for OUTPUT_IMPEDANCE attributes are RDRV_40_40, RDRV_48_48, RDRV_60_60, and RDRV_NONE_NONE.