VAR_LOAD Mode - VAR_LOAD Mode - UG861

If DELAY_TYPE is VAR_LOAD and DELAY_FORMAT is COUNT, the procedure to update the delay line follows (see the following figure):

Figure 1. VAR_LOAD Mode Using COUNT as DELAY_FORMAT

1. EN_VTC is kept Low for COUNT mode.
2. Read CNTVALUEOUT[8:0] and load the value into a register.
3. Check if updating the delay line is necessary.
4. Calculate the new delay value to be written in the delay line.
5. Put the new delay line value on the CNTVALUEIN[8:0] bus.
6. Wait for at least one clock cycle and pulse LOAD High for a clock cycle.
7. (Option for multiple updates) Wait at least four clock cycles.
8. (Option for multiple updates) Assign a new value to CNTVALUEIN.
9. (Option for multiple updates) Wait for one clock cycle and pulse LOAD High for a clock cycle.
10. (Option for multiple updates) Go back to step 7 for multiple updates.

To calculate new values to be written in delay lines, the following details must be known:

• A delay line has 512 taps and is at least 1100 ps for Spartan UltraScale+ devices.
• The delay range of a single tap is specified in the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) .

Delay lines are not calibrated before the FPGA is downloaded and the BISC engine has run.

As such the real delay of a single tap in an FPGA is unknown.

In TIME mode:

• The initial DELAY_VALUE, in the design attribute, must be provided in ps.
• Afterward, the initial delay setting can be modified by writing a value represented as a number of taps into the delay line.
• The BISC process uses a number of taps of an input delay line to eliminate the insertion delay difference between the data and the clock at the first data capture flip-flops of the receiver. This delay is called Align_Delay. Total delay provided by IDELAYE3 is the sum of the Align_Delay and DELAY_VALUE.
• The Align_Delay can be between 45 and 65 taps. It averages 50 to 54 taps.
• When writing all zeros or an amount of taps smaller than the reported Align_Delay to an input delay line, the tuned Align_Delay is impacted.
• An output delay line does not have this feature so the total output delay provided by ODELAY is equal to the DELAY_VALUE, because the output flip-flops act before the output delay line and BISC does not need to run tuning for the middle of the data eye.
• The BISC process is always running in the background to compensate for voltage and temperature variations.

In COUNT mode:

• The initial DELAY_VALUE, in the design attribute, must be provided in taps.
• The BISC procedure is not used and the real delay value of a tap cannot be known.
• There is no voltage and temperature compensation for the delay lines because BISC does not run.
• In COUNT mode, the delay line must be used as a delay of a maximum of 512 taps.
• Measurements and adjustments must be calculated in taps. For example:
  • A measurement of a data eye is expressed as 450 taps.
  • Jitter between two data eyes is expressed as 31 taps.

When DELAY_TYPE is VAR_LOAD and DELAY_FORMAT is COUNT, a delay line is used in bare-metal mode, because only the depth or amount of taps of the delay line are important.

Thus, this is the only parameter a design using COUNT mode must take care of. The value of a measured data, clock, or strobe eye is expressed as an amount of taps without providing the delay this represents. It is thus not necessary to calculate the delay of a single tap, and all 512 provided taps in a delay line are available to the user.

When DELAY_TYPE is VAR_LOAD and DELAY_FORMAT is TIME, the Align_Delay must be measured and the single tap delay must be calculated if a new delay time must be set into a delay line. Two input delay lines must be used to calculate the delay value of a single tap.

When using single-ended inputs, two inputs are necessary to calculate the single tap delay, because behind each input pad with input buffer (IBUF) there is an IDELAYE and a ISERDESE (see the following figure).

When using differential inputs, a single data channel input can be used to calculate the single tap delay. A differential input occupies two pads and thus it also covers two IDELAY/ISERDES. When a normal differential input buffer (IBUFDS) is used, only the even ISERDES of the two is used. When using a differential input buffer with differential output (IBUFDS_DIFF_OUT), you can use both ISERDESs covered by the two input pads. This is the solution for measuring a single tap value for a single differential data channel (see the following figure).

Figure 2. Two Single-ended or One Differential RX Channel

To measure Align_Delay and calculate a single tap delay:

1. In the HDL design, for the even bit slice, set the DELAY_VALUE to zero.
2. In the HDL design, for the odd bit slice, set the DELAY_VALUE to a larger non-zero value, for example 700 ps.
3. When the design is downloaded and running in an FPGA, read CNTVALUEOUT of both delay lines and store the amount of taps obtained in a set of registers.

   The tap value from the even bit slice is the Align_Delay and that from the odd bit slice is the total delay value (Align_Delay + Requested value = Total_Value).

4. The requested delay value, 700 ps in this case, is represented by the following equation:
   Total_Value – Align_Delay = n taps
5. The delay of a single tap is then equal to the following equation:
   odd channel DELAY_VALUE / n taps = single tap
6. The new CNTVALUEIN value to write to the delay line or lines used in taps is shown in the following equation for IDELAYs or the second equation for ODELAYs:
   CNTVALUEIN <IDELAY> = (wanted delay / single tap) + Align_Delay
   CNTVALUEIN <ODELAY> = (wanted delay / single tap)
7. Write this new value in the delay line using the delay line update procedure.

Figure 3. Changing Delay when DELAY_TYPE = VAR_LOAD