VARIABLE Mode - VARIABLE Mode - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

The DELAY_TYPE attribute set to VARIABLE selects the variable tap delay line (Table 1). In VARIABLE mode, the CE and INC pins are used to manually increment and decrement the delay line tap per tap (INC/DEC increments or decrements one tap at a time). The tap delay increments by setting CE = 1 and INC = 1, or decrements by CE = 1 and INC = 0. The increment/decrement operation depends on the UPDATE_MODE attribute (see Figure 1). The RXTX_BITSLICE.EN_VTC pin should be held Low during the delay change command to ensure that any automatic adjustments are stopped.

To increment/decrement delay lines when using TIME mode:

  1. Deassert (Low) the RXTX_BITSLICE.EN_VTC pin.
  2. Wait a minimum of 10 clock cycles.
  3. Use the CE and INC ports to increment or decrement the delay line.
  4. Wait a minimum of 10 clock cycles.
  5. Assert the RXTX_BITSLICE.EN_VTC pin.

In COUNT mode, the RXTX_BITSLICE.EN_VTC port is always Low after the reset sequence has completed. Use the preceding TIME mode procedure, step 2 through step 4.

Table 1. RXTX_BITSLICE Control Pin when DELAY_TYPE = VARIABLE 1
EN_VTC CLK LOAD CE INC Tap Setting
1 1/0 X X X Not supported, EN_VTC must be Low when LOAD, CE, and INC are active.
0 0 X X X No change
0 1 0 0 X No change
0 1 0 1 1 Current value + 1 tap 2
0 1 0 1 0 Current value – 1 tap 2
0 1 0 0 0 No change
  1. Only valid port combinations are provided in the table.
  2. Value depends upon the UPDATE_MODE attribute. See the following figure.
Figure 1. Variable Mode, UPDATE_MODE = ASYNC

Notes on the preceding figure:

  • At the rising edge of clock event 7, CE and INC are both High. The current tap is incremented by one because the INC signal is High for two clock cycles while CE only is High for a single cycle. UPDATE_MODE = ASYNC. The new setting is represented by Val_x+1.
  • At the rising edge of clock event 13, CE is High and INC is Low. The delay line is decremented by one tap. The DATAOUT again has taken the position of the first loaded value.
  • At the rising edge of clock event 19, CE and INC are both High. The current tap is incremented by one because the INC signal is High for two clock cycles while CE is High only for a single cycle. UPDATE_MODE = ASYNC. The new setting is represented by Val_x+1.