Uncalibrated Source Termination in HP I/O Banks - Uncalibrated Source Termination in HP I/O Banks - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document_ID
UG861
Release_Date
2026-04-28
Revision
1.1 English

HP I/O banks have an optional uncalibrated source termination feature for SSTL, HSTL, POD, and HSUL standards that is similar to DCI. This feature provides an option of a 40 Ω, 48 Ω, or 60 Ω driver for the supported standards to match the characteristic impedance of the driven line.

An important difference between this uncalibrated option and DCI is that instead of calibrating to an external reference resistor on the VRP pin when using DCI, the uncalibrated source termination feature invokes internal resistors determined by the OUTPUT_IMPEDANCE attribute where no calibration routine is available to compensate for temperature, process, or voltage variations.

Important: This feature is only available in HP I/O banks.

The allowed values for OUTPUT_IMPEDANCE are RDRV_40_40, RDRV_48_48, or RDRV_60_60.

The main difference in how DCI or uncalibrated termination is invoked in a design is determined when choosing to use either a DCI I/O standard or an uncalibrated one. In both DCI and uncalibrated I/O standards, source termination value is determined by the attribute OUTPUT_IMPEDANCE.

The following table shows a list of I/O standards that support uncalibrated source termination in HP I/O banks.

Note: HD I/O banks do not support source termination control.
Table 1. I/O Standards that Support Uncalibrated Source Termination in HP I/O Banks
HSTL DIFF_HSTL SSTL DIFF_SSTL POD/HSUL DIFF_POD
HSTL_I DIFF_HSTL_I SSTL18_I DIFF_SSTL18_I POD12 DIFF_POD12
HSTL_I_18 DIFF_HSTL_I_18 SSTL15 DIFF_SSTL15 POD10 DIFF_POD10
HSTL_I_12 DIFF_HSTL_I_12 SSTL135 DIFF_SSTL135 HSUL_12 DIFF_HSUL_12
    SSTL12 DIFF_SSTL12