Transmitter Setup - Transmitter Setup - UG861

The transmitter in the RXTX_BITSLICE has an 8-bit input parallel register. In 4-bit mode, only bits [3:0] are used to store the data from the logic. Capturing the parallel data and the clocking of registers in the RXTX_BITSLICE happens on internally generated clocks. To create these clocks, the transmitter side of the RXTX_BITSLICE uses the high-speed PLL generated master clock (PLL_CLK). Follow the Native Mode Bring-up and Reset procedure described for the BITSLICE_CONTROL primitive.

The 8-bit input register multiplexes down to a registered 4-bit and then to a registered 2-bit value. Those two bits of data pass through a multiplexer and register into the output delay line. The output delay line connects to an output buffer in the IOB (see the following figure).

The RXTX_BITSLICE has a loopback attribute allowing the output of the transmitter at the output of the delay line to be looped back to the receiver at the input of the delay line.

Both 3-state possibilities are passing through the transmitter (see the preceding figure). The chosen 3-state option is set in the transmitter by the TBYTE_CTL attribute.

• The transmitter operates on the high-speed clock supplied to the BITSLICE_CONTROL.PLL_CLK input. In the BITSLICE_CONTROL primitive, a clock generator ensures all clocks for the transmitter are generated.
• The PLL_CLK is best generated by one of the two PLLs behind the I/O bank in the same clock area. When following the Native Mode Bring-up and Reset section of the BITSLICE_CONTROL section, the FPGA interconnect and internal RXTX_BITSLICE clocks are aligned.
• Data presented to the RXTX_BITSLICE.D inputs is captured in the bit slice and serialized to the bit slice output by clocks generated in BITSLICE_CONTROL.
• This data, 8-bit or 4-bit wide, is serialized and transmitted at the rate of the applied BITSLICE_CONTROL.PLL clock.
• The transmitter part of the RXTX_BITSLICE or TX_BITSLICE is normally used to serially transmit data bits, but when the bit slice D-inputs are pulled to a static level, it is possible to generate and transmit any predicted signal format. A 50/50 clock pattern is generated when the D[7:0] or D[3:0] inputs are pulled to 10101010 or 1010.
• The OUTPUT_PHASE_90 attributes in each transmitter provide help generating phase-aligned data and clocks or 90-degree shifted data or clock setups.

Latency through the transmitter:

• With OUTPUT_PHASE_90 = FALSE, the latency from loading eight parallel bits to a first serial output bit is shown in the following equation for 8-bit (see the following figure):
  T + (13/16)T = latency

  where T is the period of the parallel load or interconnect logic clock, and shown in the following equation for 4-bit (see the figure next to the following figure):

  T + (5/8)T = latency
• With OUTPUT_PHASE_90 = TRUE, the latency from loading eight parallel bits to a first serial output bit is shown in the following equation for 8-bit (see the following figure):
  T + (14/16)T = latency

  where T is the period of the parallel load or interconnect logic clock, and shown in the following equation for 4-bit (see the figure next to the following figure):

  1T + (6/8)T = latency

  where T is the period of the parallel load or FPGA logic clock.

For the TX_BITSLICE, the Fabric Clock does not directly connect to the TX_BITSLICE. The PLL and BITSLICE_CONTROL create a divided clock. When DATA_WIDTH=4, the divided clock is inverted. Transmitting clock and data are similar operations, so the same clocking rules must be followed:

• Transmitting a clock can be done from any of the RXTX_BITSLICEs in a nibble.
• The generated clock depends on the pattern applied at the D[7:0] pins of the transmitter.
• For example, when 01010101 is applied, a 50/50 clock with frequency equal to half the RXTX_BITSLICE.PLL_CLK is generated.
• Assume an output data rate of 1250 Mb/s is required and a clock must be generated, too.
• 1250 Mb/s requires a PLL generated high-speed clock of 1250 MHz connected at the BITSLICE_CONTROL.PLL_CLK.