The AMD 7 series architecture supported T_DCI standards for bidirectional SSTL I/O configurations with 3-state support for internal input split-termination. Those T_DCI standards are not supported in Spartan UltraScale+ devices. However, in HP and XP5IO banks, internally terminated SSTL12 standards are capable of supporting similar bidirectional configurations. For example, in 7 series FPGAs, SSTL12_T_DCI has the same functionality as SSTL12_DCI in HP I/O banks or SSTL12 in XP5IO I/O banks.