The SSTL for 1.8V (SSTL18), 1.5V (SSTL15), 1.35V (SSTL135) and 1.2V (SSTL12) are I/O standards used for general-purpose memory buses. While example termination techniques are discussed in this section, the optimal termination schemes for a given memory interface are determined using signal-integrity analysis of the actual PCB topology including the memory devices used, the board layout, and transmission line impedances. AMD provides IBIS model files for these I/O standards. SSTL standards are supported for both single-ended signaling and differential signaling. The differential versions use a true differential amplifier input buffer and complementary push-pull output buffers. Calibrated termination for these standards are the preferred I/O standards to use for memory interfaces implemented in the HP and XP5IO I/O banks.
SSTL18 is defined by the JEDEC standard JESD8-15, and is used for DDR2 SDRAM interfaces. For some topologies (such as short, point-to-point interfaces), the class-I driver can result in reduced overshoot and better signal integrity.
SSTL18 class-I is available in both the HP and HD I/O banks. Both HP and HD I/O banks provide ODT attributes for untuned internal parallel split-termination resistors for the non-DCI versions of these standards. In addition, the source termination feature (OUTPUT_IMPEDANCE — HP I/O only) provides the option of 40 Ω, 48 Ω, or 60 Ω tuned driver impedance in HP I/O banks in both DCI and non-DCI versions. The driver output impedance is set to a default of 40 Ω (48 Ω for HD I/O). The optimal drive and termination scheme for any new design is determined through careful signal-integrity analysis. SSTL18 class-I is only available as an input in HD I/O banks. HD I/O banks provide the option of ODT attributes for untuned internal parallel split-termination resistors for the standard.
SSTL15 is typically used for DDR3 SDRAM interfaces and is roughly defined (not by name) in the JEDEC standard JESD79-3E. For this standard, the full-strength driver (SSTL15) is available in both the HP, HD, and XP5IO I/O banks. For some topologies (such as short point-to-point interfaces), the reduced-strength driver can result in reduced overshoot and better signal integrity. The HP and XP5IO I/O banks provide DCI options for tuned internal parallel split-termination resistors. HP and HD I/O banks provide options for untuned internal parallel split-termination resistors (using the ODT attributes). In addition, the source termination feature (OUTPUT_IMPEDANCE) provides the option of 40 Ω, 48 Ω, or 60 Ω tuned driver impedance in HP I/O banks in both DCI and non-DCI versions. When XP5IO I/O enable ODT or OUTPUT_IMPEDANCE, termination circuits are always calibrated. The driver output impedance is set to a default of 40 Ω (48 Ω for HD I/O banks). The optimal drive and termination scheme for any new design is determined through careful signal-integrity analysis.
SSTL135 is used for DDR3L SDRAM interfaces and is roughly defined (not by name) in the JEDEC standard JESD79-3-1. For this standard, the full-strength driver (SSTL135) is available in both the HP and HD I/O banks. For some topologies (such as short point-to-point interfaces), the reduced-strength driver can result in reduced overshoot and better signal integrity.
SSTL12 supports Micron's next-generation RLDRAM3 memory. The DCI option is available to improve the signal integrity through the use of tuned internal split-termination resistors in HP and XP5IO I/O banks. HP I/O banks also provide the ODT attribute options for untuned internal parallel split-termination resistors. In addition, the source termination feature (OUTPUT_IMPEDANCE) provides the option of 40 Ω, 48 Ω, or 60 Ω tuned driver impedance in HP I/O banks in both DCI and non-DCI versions. When XP5IO I/O enable ODT or OUTPUT_IMPEDANCE, termination circuits are always calibrated. The driver output impedance is set to a default of 40 Ω. HD I/O banks only support SSTL12 as an input. The optimal drive and termination scheme for any new design is determined through careful signal-integrity analysis.