Split-Termination DCI (Thevenin Equivalent Termination to VCCO/2) - Split-Termination DCI (Thevenin Equivalent Termination to VCCO/2) - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

Some I/O standards (HSTL and SSTL) require an input termination resistance (R) to a VTT voltage of VCCO/2 (see the following figure).

Figure 1. Input Termination to VCCO / 2 without DCI (where R = Z0 )

Split-termination DCI creates a Thevenin equivalent circuit using two resistors of twice the resistance value (2R). One terminates to VCCO, the other to GND. Split-termination DCI provides an equivalent termination to VCCO/2 using this method. The 2R termination resistance is set by programming the ODT attribute. The resistors to VCCO and GND are equal to twice the value set by ODT. For example, to achieve the Thevenin equivalent parallel-termination circuit of approximately 50 Ω to VCCO/2, a 240 Ω external precision resistor is required at the VRP pin and ODT is set to RTT_48. Possible values for ODT for split-termination DCI are RTT_40, RTT_48, or RTT_60.

In HP banks, the following IOSTANDARDS must be used to trigger split input termination.

Table 1. HP DCI I/O Standards Supporting Split-Termination DCI
HSTL DIFF_HSTL SSTL DIFF_SSTL
HSTL_I_DCI DIFF_HSTL_I_DCI SSTL18_I_DCI DIFF_SSTL18_I_DCI
HSTL_I_DCI_18 DIFF_HSTL_I_DCI_18 SSTL15_DCI DIFF_SSTL15_DCI
    SSTL135_DCI DIFF_SSTL135_DCI
    SSTL12_DCI DIFF_SSTL12_DCI

In XP5IO banks, the following IOSTANDARDS must be used to trigger split input termination.

Table 2. XP5IO DCI I/O Standards Supporting Split-Termination DCI
HSTL DIFF_HSTL SSTL DIFF_SSTL HSLVDCI
HSTL_I DIFF_HSTL_I SSTL15 DIFF_SSTL15 HSLVDCI_15
HSTL_I_12 DIFF_HSTL_I_12 SSTL135 DIFF_SSTL135  
    SSTL12 DIFF_SSTL12  

The following figure illustrates split-termination DCI.

Figure 2. Input Termination to VCCO/ 2 Using Split-Termination DCI (where R = Z0 )