All Spartan UltraScale+ devices have configurable SelectIO interface drivers and receivers, supporting a wide variety of standard interfaces. The robust feature set includes programmable control of output strength and slew rate, on-chip termination, and the ability to internally generate a reference voltage (INTERNAL_VREF). Each bank type in the Spartan UltraScale+ device might not support all features and IOSTANDARDs.
Bank Differences
The following figure shows an overview of the HP, HD, and XP5IO banks to illustrate bank differences.
The following figure illustrates the general IOB structure that applies to all three bank types.
HP I/O Bank Overview
With some exceptions, each HP I/O bank contains 52 SelectIO pins, where 48 can implement both single-ended and differential I/O standards. The other four pins, including the multipurpose VRP pin, are single-ended (only) IOBs. Every HP I/O SelectIOresource contains input, output, and 3-state drivers.
The SelectIO pins can be configured to various I/O standards, both single-ended and differential.
- Single-ended I/O standards are, for example, LVCMOS, HSTL, SSTL, HSUL, and POD.
- Differential I/O standards are, for example, MIPI D-PHY, LVDS, and differential HSTL, POD, HSUL, and SSTL.
When not used as a VRP pin, the multipurpose VRP pin in each bank can only be used with single-ended I/O standards. Each HP bank contains an optional VREF pin which can be used to provide an external VREF source to inputs that leverage VREF to define their switching thresholds. Figure 1 shows the relative location of the single-ended IOBs within a bank. When not configured, I/O drivers are 3-stated and I/O receivers are weakly pulled down. Figure 2 shows the single-ended (only) HP I/O block (IOB) and its connections to the internal logic and the device pad. Figure 3 shows the standard HP IOB.
Each HP IOB has a direct connection to bit slice components containing the input and output resources for serialization, deserialization, signal delay, clock, data, and 3-state control, and registering for the IOB. The bit slice components can be used in Component mode individually as IDELAY, ODELAY, ISERDES, OSERDES, and input and output registers. They can also be used at a lower granularity level as RX_BITSLICE (input), TX_BITSLICE (output), and RXTX_BITSLICE (bidirectional) components where all of the bit slice functions are grouped together in a single interface. See HP I/O Bank SelectIO Interface Logic Resources for more information.
HD I/O Bank Overview
HD I/O banks are grouped into 42 I/O pins capable of either 42 single-ended signals, or 21 differential signals. HD I/O support both single-ended and differential signaling capabilities and have input, output, and 3-state driver conditions. HD I/O only support internal VREF and uncalibrated termination so there are no dedicated pins, and each non-supply pin can function as a single-ended or differential I/O. Within a bank there are two HDGC pin pairs which can function as a normal I/O but also have dedicated connections to the global clock network. HDGC pins can function in both differential or single-ended signal standards. When used as a single-ended signaling standard, only the positive side of the differential pair can connect directly to the global clocking network.
The HD I/O SelectIO pins can be configured to various I/O standards, both single-ended and differential.
- Single-ended I/O standards are, for example, LVCMOS, LVTTL, HSTL, and SSTL.
- Differential I/O standards that support drive and receive capabilities are differential HSTL and SSTL.
- Differential I/O standards that are input only are LVDS and LVPECL.
The IOB diagrams above shows the standard HD IOB but do not support the DCITERMDISABLE port, only INTERMDISABLE. When not configured, I/O drivers are 3-stated, and I/O receivers are weakly pulled-down.
Each HD IOB has a direct connection to input and output register resources for clock, data, and 3-state control. See HD I/O Interface Logic Resources for more information.
XP5IO I/O Bank Overview
The XP5IO I/O banks (when present) are optimized to provide Spartan UltraScale+ devices with a high-speed PHY that can interface with high-speed interfaces used in LPDDR5 and MIPI D-PHY interfaces. The XP5IO I/O bank is grouped into 11 nibbles of six I/O pins, giving a total of 66 I/O pins capable of either 66 single-ended signals, or 33 differential signals. XP5IO I/O support both single-ended and differential signaling capabilities and have input, output, and 3-state driver conditions. XP5IO I/O only support internal VREF and require a single termination reference (VR) for all XP5IO banks in a device. A bank contains four dedicated connections to the global clock network (GC). There are four clock-capable I/O (CCIO) pins (two I/O pin pairs) in octads 4, 5, 6, and 10, but within these octads only one of the CCIO can be used. CCIO pins can function in both differential or single-ended signal standards. When used as a single-ended signaling standard, only the positive side of the differential pair can connect directly to the global clocking network.
The XP5IO SelectIO pins can be configured to various I/O standards, both single-ended and differential, powered from 1.0V to 1.5V:
- Single-ended I/O standards are LVCMOS, HSTL, SSTL, POD, and LVSTL.
- Differential I/O standards that support drive and receive capabilities are differential HSTL, SSTL, POD, LVSTL, LVDS, and MIPI_DPHY.
There are no dedicated low-speed register resources in the XP5IO, so when the PHY is bypassed, only direct access to programmable fabric resources is available, leaving the XP5IO only suitable for very low performance when not used with the PHY. See XP5IO I/O Interface Logic Resources for more information.