SSTL18_I, DIFF_SSTL18_I - SSTL18_I, DIFF_SSTL18_I - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English
Table 1. Available I/O Bank Type
HD HP
Available Available

Class-I drivers can be preferred for short, point-to-point board topologies. Parallel end-termination resistors (commonly 50 Ω) to VTT = (VCCO/2) are typically placed on the board close to any receiver. Optional untuned split input ODT provides Thevenin equivalent resistance of R (where R = Z0) to the VCCO/2. The untuned on-die source termination feature (OUTPUT_IMPEDANCE) provides the option of 40 Ω, 48 Ω, or 60 Ω of driver impedance in HP I/O banks. The driver output impedance is set to a default of 40 Ω (48 Ω for HD I/O). The differential (DIFF_) version uses complementary single-ended drivers for outputs, and differential receivers for inputs.