SSTL18, SSTL15, SSTL135, SSTL12 Termination - SSTL18, SSTL15, SSTL135, SSTL12 Termination - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

The following figure shows a sample circuit illustrating a unidirectional termination technique for SSTL18, SSTL15, SSTL135, or SSTL12. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (that is, SSTL12 should only interface with SSTL12).

Figure 1. SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional Termination

The following figure shows a sample circuit illustrating a bidirectional termination technique for SSTL18, SSTL15, SSTL135, or SSTL12. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (that is, SSTL12 should only interface with SSTL12).

Figure 2. SSTL18, SSTL15, SSTL135, or SSTL12 Bidirectional Termination

The following figure shows a sample circuit illustrating a bidirectional termination technique for SSTL18, SSTL15, SSTL135, or SSTL12 with DCI. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (that is, SSTL12_DCI should only interface with SSTL2_DCI). DCI standards are only supported in HP I/O banks.

Figure 3. SSTL18_DCI, SSTL15_DCI, SSTL135_DCI, or SSTL12_DCI Bidirectional Termination