SSTL15_DCI, SSTL135_DCI, SSTL12_DCI, DIFF_SSTL15_DCI, DIFF_SSTL135_DCI, DIFF_SSTL12_DCI - SSTL15_DCI, SSTL135_DCI, SSTL12_DCI, DIFF_SSTL15_DCI, DIFF_SSTL135_DCI, DIFF_SSTL12_DCI - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English
Table 1. Available I/O Bank Type
HD HP
N/A Available

The DCI standards provide tuned internal parallel split-termination resistors that are always present at the receivers. The value of both the resistance set by the ODT attributes, creates the Thevenin equivalent of R (where R = Z0) to the VCCO/2 mid-point level. The source termination feature (OUTPUT_IMPEDANCE) provides the option of 40 Ω, 48 Ω, or 60 Ω tuned driver impedance in HP I/O banks. The driver output impedance is set to a default of 40 Ω. The differential (DIFF_) versions use complementary single-ended drivers for outputs, and differential receivers for inputs.