In SAME_EDGE_PIPELINED mode, the data is presented into the device logic on the same clock edge. Unlike the SAME_EDGE mode, the data pair is not separated by one clock cycle. However, additional clock latency is required to remove the separated effect of the SAME_EDGE mode. The following figure shows the timing diagram of the input DDR using the SAME_EDGE_PIPELINED mode. The output pairs Q1 and Q2 are presented to the device logic at the same time.
Figure 1. Input DDR Timing in SAME_EDGE_PIPELINED Mode
The following figure shows a block diagram of the IDDRE1 primitive.
Figure 2. IDDRE1 Primitive Block Diagram
