Rules for Combining I/O Standards in the Same Bank - Rules for Combining I/O Standards in the Same Bank - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

The following rules must be obeyed to combine different input, output, and bidirectional standards in the same bank:

  1. Combining output standards only. Output standards with the same output VCCO requirement can be combined in the same bank.

    Compatible example:

    SSTL15_I and LVDCI_15 outputs

    Incompatible example:

    SSTL15 (output VCCO = 1.5V) and LVCMOS18 (output VCCO = 1.8V) outputs

    Only one true differential output I/O standard can be used in HP I/O banks. LVDS with LVDS_PRE_EMPHASIS = FALSE (default) and LVDS with LVDS_PRE_EMPHASIS = TRUE are considered as two different true-differential output standards and cannot be combined within the same HP I/O bank.

  2. Combining input standards only. Input standards with the same VCCO and VREF requirements can be combined in the same bank.

    Compatible example:

    LVCMOS15 and HSTL_I inputs

    Incompatible example:

    LVCMOS15 (input VCCO = 1.5V) and LVCMOS18 (input VCCO = 1.8V) inputs

    Incompatible example:

    HSTL_I_DCI_18 (VREF = 0.9V) and HSTL_I_DCI (VREF = 0.75V) inputs

  3. Combining input standards and output standards. Input standards and output standards with the same VCCO requirement can be combined in the same bank.

    Compatible example:

    LVDS_25 input and LVCMOS25 output

    Incompatible example:

    LVCMOS18 output (output VCCO = 1.8 V) and HSTL_I output (input VCCO = 1.5 V)

  4. Combining bidirectional standards with input or output standards. When combining bidirectional I/O with other standards, make sure the bidirectional standard can meet the first three rules.

The implementation tools enforce these design rules.

The following table summarizes the VCCO and VREF requirements for each supported I/O standard. For more detailed DC specifications, including the recommended operating ranges of the supplies for each supported I/O standard, see the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) .

Table 1. VCCO and VREF Requirements for Each Supported I/O Standard
I/O Standard I/O Bank Availability VCCO (V) VREF (V)
Output Input Input with DIFF_TERM_ADV and DIFF_TERM Support Input
LVTTL HD 3.3 3.3 N/A N/A
LVCMOS33 HD 3.3 3.3 N/A N/A
LVCMOS25 HD 2.5 2.5 N/A N/A
LVCMOS18 HP/HD 1.8 1.8 N/A N/A
LVCMOS15 HP/HD/XP5IO 1.5 1.5 N/A N/A
LVCMOS12 HP/HD/XP5IO 1.2 1.2 N/A N/A
HSUL_12 HP/HD/XP5IO 1.2 1.2 N/A 0.60
LVDCI_18 HP 1.8 1.8 N/A N/A
LVDCI_15 HP 1.5 1.5 N/A N/A
HSUL_12_DCI HP/HD 1.2 1.2 N/A 0.60
HSLVDCI_18 HP 1.8 1.8 N/A 0.90
HSLVDCI_15 HP/XP5IO 1.5 1.5 N/A 0.75
HSTL_I HP/HD/XP5IO 1.5 1.5 N/A 0.75
HSTL_I_DCI HP 1.5 1.5 N/A 0.75
HSTL_I_18 HP/HD 1.8 1.8 N/A 0.90
HSTL_I_DCI_18 HP 1.8 1.8 N/A 0.90
HSTL_I_12 HP/XP5IO 1.2 1.2 N/A 0.60
HSTL_I_DCI_12 HP 1.2 1.2 N/A 0.60
LVSTL05_10 XP5IO 1.0 1.0 N/A 0.125
LVSTL06_12 XP5IO 1.2 1.2 N/A 0.150
LVSTL_11 XP5IO 1.1 1.1 N/A 0.183
POD10 HP/XP5IO 1.0 1.0 N/A 0.70
POD12 HP/XP5IO 1.2 1.2 N/A 0.84
POD10_DCI HP 1.0 1.0 N/A 0.70
POD12_DCI HP 1.2 1.2 N/A 0.84
SSTL18_I HP/HD 1.8 1.8 N/A 0.90
SSTL15 HP/HD/XP5IO 1.5 1.5 N/A 0.75
SSTL135 HP/HD/XP5IO 1.35 1.35 N/A 0.675
SSTL12 HP/HD/XP5IO 1.2

(N/A for HDIO)

1.2 N/A 0.60
SSTL18_I_DCI HP 1.8 1.8 N/A 0.90
SSTL15_DCI HP 1.5 1.5 N/A 0.75
SSTL135_DCI HP 1.35 1.35 N/A 0.675
SSTL12_DCI HP 1.2 1.2 N/A 0.60
DIFF_HSTL_I HP/HD/XP5IO 1.5 1.5 2 N/A N/A
DIFF_HSTL_I_18 HP/HD 1.8 1.8 2 N/A N/A
DIFF_SSTL18_I HP/HD 1.8 1.8 2 N/A N/A
DIFF_HSUL_12 HP/HD/XP5IO 1.2 1.2 3 N/A N/A
DIFF_HSTL_I_DCI HP 1.5 1.5 N/A N/A
DIFF_HSTL_I_DCI_18 HP 1.8 1.8 N/A N/A
DIFF_HSTL_I_12 HP/XP5IO 1.2 1.2 2 N/A N/A
DIFF_HSTL_I_DCI_12 HP 1.2 1.2 N/A N/A
DIFF_LVSTL05_10 XP5IO 1.0 1.0 N/A N/A
DIFF_LVSTL06_12 XP5IO 1.2 1.2 N/A N/A
DIFF_LVSTL_11 XP5IO 1.1 1.1 N/A N/A
DIFF_POD10 HP/XP5IO 1.0 1.0 2 N/A N/A
DIFF_POD12 HP/XP5IO 1.2 1.2 2 N/A N/A
DIFF_POD10_DCI HP 1.0 1.0 N/A N/A
DIFF_POD12_DCI HP 1.2 1.2 N/A N/A
DIFF_SSTL18_I_DCI HP 1.8 1.8 N/A N/A
DIFF_SSTL15_DCI HP 1.5 1.5 N/A N/A
DIFF_SSTL15 HP/HD/XP5IO 1.5 1.5 2 N/A N/A
DIFF_SSTL135 HP/HD/XP5IO 1.35 1.35 2 N/A N/A
DIFF_SSTL12 HP/HD/XP5IO 1.2

(N/A for HDIO)

1.2 2 N/A N/A
DIFF_SSTL135_DCI HP 1.35 1.35 N/A N/A
DIFF_SSTL12_DCI HP 1.2 1.2 N/A N/A
DIFF_HSUL_12_DCI HP 1.2 1.2 N/A N/A
LVDS_25 HD N/A 2.5 1 N/A N/A
LVDS15 XP5IO 1.5 1.5 1.5 N/A
LVDS HP 1.8 1.8 1 1.8 N/A
LVPECL HD N/A Any N/A N/A
SLVS_400_18 HP N/A 1.8 1 1.8 N/A
MIPI_DPHY_DCI HP 1.2 1.2 1.2 N/A
MIPI_DPHY XP5IO 1.2 1.2 1.2 N/A
SLVS_400_25 HD N/A 2.5 1 N/A N/A
SUB_LVDS HP/HD 1.8

(N/A for HDIO)

1.8 1 1.8 (HP Only) N/A
  1. Differential inputs for these standards can be placed in banks with VCCO levels that are different from the required level for outputs. Some important criteria to consider:
    1. The optional internal differential termination is not used, DIFF_TERM_ADV = TERM_NONE or DIFF_TERM = FALSE (default value), unless the VCCO voltage is at the level required for outputs.
    2. The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) .
    3. The differential signals at the input pins meet the VIDIFF and VICM requirements in the DC Specifications tables in the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) . In some cases, to accomplish this it might be necessary to provide an external circuit to both AC-couple and DC-bias the pins.
  2. When on-die input termination is used (ODT is set to a value other than RTT_NONE) or when DQS_BIAS = TRUE, the VCCO input voltage is as specified. When ODT = RTT_NONE and DQS_BIAS = FALSE, the VCCO input voltage is any allowed voltage.
  3. When on-die input termination is used (ODT value set to something other than RTT_NONE) or when DQS_BIAS is set to TRUE, the VCCO input voltage is 1.2V for HP I/O banks.
  4. If the VCCO voltage exceeds 2.85V, the outputs are 3-stated. The device should always be operated within the recommended operating range as specified in the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) .

The following table summarizes the DRIVE and SLEW attribute options, bidirectional buffer availability, and DCI termination type for each supported I/O standard.

Table 2. Attribute Options, Bidirectional Buffer Availability, and DCI Termination Type
I/O Standard I/O Bank Type Output Slew Output Drive Bidirectional Buffers 1 Termination Type 2
HD I/O Banks HP and XP5IO I/O Banks HD I/O Banks HP and XP5IO I/O Banks Input Output 3
Allowed Values Default Allowed Values Default Allowed Values Default Allowed Values Default
LVTTL HD

SLOW

FAST

SLOW N/A 4, 8, 12 12 N/A Yes None None
LVCMOS33 HD

SLOW

FAST

SLOW N/A 4, 8, 12 12 N/A Yes None None
LVCMOS25 HD

SLOW

FAST

SLOW N/A 4, 8, 12 12 N/A Yes None None
LVCMOS18 HP/HD

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW 4, 8, 12 12 2, 4, 6, 8, 12 12 Yes None None
LVCMOS15 HP/HD/XP5IO

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW 4, 8, 12 12 2, 4, 6, 8, 12 12 Yes None None
LVCMOS12 HP/HD/XP5IO

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW 4, 8 12 2, 4, 6, 8 12 Yes None None
HSUL_12 HP/HD/XP5IO

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes   Driver
LVDCI_18 HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes None Driver
LVDCI_15 HP/XP5IO N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes None Driver
HSUL_12_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single Driver
HSLVDCI_18 HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes None Driver
HSLVDCI_15 HP/XP5IO N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes None Driver
HSTL_I HP/HD/XP5IO

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
HSTL_I_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
HSTL_I_18 HP/HD

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
HSTL_I_DCI_18 HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
HSTL_I_12 HP/XP5IO N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
HSTL_I_DCI_12 HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
LVSTL05_10 XP5IO

SLOW

FAST

SLOW FAST FAST N/A N/A Yes Split Driver
LVSTL06_12 XP5IO

SLOW

FAST

SLOW FAST FAST N/A N/A Yes Split Driver
LVSTL_11 XP5IO

SLOW

FAST

SLOW FAST FAST N/A N/A Yes Split Driver
POD10 HP/XP5IO N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
POD12 HP/XP5IO N/A

SLOW

(HP only)

MEDIUM (HP only)

FAST

FAST N/A N/A Yes Split Driver
POD10_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
POD12_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
SSTL18_I HP/HD N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
SSTL15 HP/HD/XP5IO

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
SSTL135 HP/HD/XP5IO

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
SSTL12 HP/HD/XP5IO

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
SSTL18_I_DCI HP

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
SSTL15_DCI HP

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
SSTL135_DCI HP

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
SSTL12_DCI HP

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single 4 Driver 4
DIFF_HSTL_I HP/HD/XP5IO

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
DIFF_HSTL_I_18 HP/HD

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
DIFF_SSTL18_I HP/HD

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
DIFF_HSUL_12 HP/HD/XP5IO

SLOW

FAST

SLOW

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
DIFF_HSTL_I_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
DIFF_HSTL_I_DCI_18 HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Split Driver
DIFF_HSTL_I_12 HP/XP5IO N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single Driver
DIFF_HSTL_I_DCI_12 HP N/A N/A N/A N/A No None None
DIFF_LVSTL05_10 XP5IO N/A FAST FAST N/A N/A Yes 4 None None
DIFF_LVSTL06_12 XP5IO N/A FAST FAST N/A N/A No None None
DIFF_LVSTL_11 XP5IO N/A FAST FAST N/A N/A No None None
DIFF_POD10 HP/XP5IO N/A

SLOW

MEDIUM

FAST

FAST N/A N/A Yes 4 None None
DIFF_POD12 HP/XP5IO N/A

SLOW

(HP only)

MEDIUM (HP only)

FAST

FAST N/A N/A Yes Split Driver
DIFF_POD10_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single Driver
DIFF_POD12_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single Driver
DIFF_SSTL18_I_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes N/A Driver
DIFF_SSTL15_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single Driver
DIFF_SSTL15 HP/HD/XP5IO N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single Driver
DIFF_SSTL135 HP/HD/XP5IO N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single Driver
DIFF_SSTL12 HP/HD/XP5IO N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single Driver
DIFF_SSTL135_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single Driver
DIFF_SSTL12_DCI HP N/A

SLOW

MEDIUM

FAST

SLOW N/A N/A Yes Single Driver
DIFF_HSUL_12_DCI HP N/A N/A N/A N/A No N/A Driver
LVDS_25 HD N/A N/A N/A N/A No N/A N/A
LVDS15 XP5IO N/A N/A N/A N/A Yes TERM_100 N/A
LVDS HP N/A N/A N/A N/A Yes TERM_100 N/A
LVPECL HD N/A N/A N/A N/A No N/A N/A
SLVS_400_18 HP N/A N/A N/A N/A No TERM_100 N/A
MIPI_DPHY_DCI HP N/A N/A N/A N/A No TERM_100 Driver
MIPI_DPHY XP5IO N/A N/A N/A N/A No TERM_100 Driver
SLVS_400_25 HD N/A N/A N/A N/A No N/A N/A
SUB_LVDS HP/HD N/A N/A N/A N/A

Yes

(HP only)

TERM_100

(HP only)

N/A
  1. The bidirectional buffers column describes the I/O standards use of a bidirectional signal.
  2. The DCI termination type column describes the type of termination available for the DCI I/O standards. Split refers to the split-termination resistors. Single refers to single resistor termination to VCCO.
  3. A value of DRIVER in this column only applies to HP I/O banks.
  4. INTERM = Single and OUTTERM = DRIVER for HP I/O banks.
  5. The bidirectional configuration on these I/O standards is a fixed impedance structure optimized to 100 Ω differential. They are intended to only be used in point-to-point transmissions that do not have turn around timing requirements.