Release Reset - Release Reset - UG861

1. Hold all the EN_VTCs High for all of the used IDELAYs and ODELAYs.
2. Use the following sequence to bring the I/O out of reset:
   1. Release the reset of the PLL/MMCM generating the clocks for the interface.
   2. Wait for the PLL/MMCM to reach the LOCKED state.
   3. Release the reset of following primitives: IDELAY, ODELAY, ISERDES, and OSERDES.
   4. After the previous step is completed, release the reset for IDELAYCTRL.
   5. Wait until the RDY of all the used IDELAYCTRL primitives are asserted High.

Now the application in the FPGA logic can be released after a delay of at least 64 clock cycles.