Release Reset - Release Reset - UG861

1. Ensure that the SELF_CALIBRATE attribute is set to ENABLE.
2. On all used RXTX_BITSLICE (RX_BITSLICE, TX_BITSLICE) primitives, hold the EN_VTC signals High.
3. EN_VTC of the BITSLICE_CONTROL should be held Low.
4. Use the following sequence to bring the I/O out of reset:
   1. Release the reset of the PLL/MMCM generating the clocks for the interface.
   2. Keep the CLKOUTPHYEN of the used PLL Low, which disables the CLKOUTPHY high-speed clock to the BITSLICE_CONTROL.PLL_CLK input. When a MMCM is used, disable the BUFGCE clock buffer delivering the BITSLICE_CONTROL.REFCLK clock.
      Note: As shown in Figure 1, strobe clocks must be disabled during the reset sequence. For systems that use the input clock as the strobe clock, bitslip will be required. The High-Speed SelectIOwizard provides the bitslip functionality.
   3. Wait for the PLL/MMCM to reach the LOCKED state.
   4. Release these reset signals: RXTX_BITSLICE.TX_RST_DLY, RXTX_BITSLICE.RX_RST_DLY, TX_BITSLICE_TRI.RST_DLY, RXTX_BITSLICE.TX_RST, RXTX_BITSLICE.RX_RST, TX_BITSLICE_TRI.RST, and/or BITSLICE_CONTROL.RST.
   5. Wait at least 64 application clock cycles (PLL/MMCM specification).
   6. Pull the CLKOUTPHYEN signal of the PLL High, which enables the CLKOUTPHY high-speed PLL output. For a MMCM, enable the BUFGCE to apply the BITSLICE_CONTROL.REFCLK.
5. Continue with the following post-reset sequence:
   1. Wait until the DLY_RDY of all the used BITSLICE_CONTROL primitives are asserted High by the running BISC controllers.
   2. After all the DLY_RDY signals are asserted High, use the RIU_CLK in a two flip-flop synchronizer circuit to pull the EN_VTC of the used BITSLICE_CONTROL High. For asynchronous RX designs, BITSLICE_CONTROL.EN_VTC is tied Low by the High-Speed SelectIO wizard.
   3. Wait until the BITSLICE_CONTROL.VTC_RDY status output of the BITSLICE_CONTROL is asserted High. VTC_RDY being High at this point means that the BISC controller in the BITSLICE_CONTROL primitive is tracking for voltage and temperature compensation.
   4. Strobe clocks can now be restarted.
      Note: For systems that cannot stop the strobe clocks during the reset sequence or for systems that have noisy strobes such as unlocked PLLs, bitslip might be required for RX_BITSLICE alignment.

At this point the application in the FPGA logic can be released.

Extra functional mode guidelines after VTC_RDY is High follow:

• RXTX_BITSLICE transmitters or TX_BITSLICEs require that the TBYTE_IN[3:0] inputs of the BITSLICE_CONTROL are pulled High. Use the VTC_RDY signal and a two register synchronizer running from the application clock to perform this action.
  Note: If the TBYTE_IN bus is used by logic in the FPGA, ensure the designed circuit allows that the guidelines provided above can be applied.
• RXTX_BITSLICE receivers or RX_BITSLICEs require that the PHY_RDEN[3:0] inputs of the BITSLICE_CONTROL are pulled High. Use the VTC_RDY signal and a two register synchronizer running from the application clock to perform this action.

Extra functional guidelines for serial mode receivers follow:

• A serial mode receiver only receives data. The data must be sampled by a PLL generated clock (PLL.CLKOUTPHY). In this case it is necessary that you adjust the input delay lines using additional logic to control the RX_BITSLICE.
• Follow the guidelines in Native Input Delay Type Usage and Native Output Delay Type Usage to adjust the delay line in a correct manner.

When an application is running in an FPGA, apply the following steps to safely reset the application and allow a correct bring-up afterward: