Register Interface Unit (RIU) - Register Interface Unit (RIU) - UG861

Using the register interface unit (RIU), the BITSLICE_CONTROL primitive can be turned into a processor peripheral block. The RIU interface is a set of 64 read/write, 16-bit registers, acting as a dynamically accessible processor peripheral interface providing full control over every function and feature of a nibble: control of all input, output, 3-state, and all delay lines (input, output and quarter), voltage and temperature (VT) tracking, clocking options, and built-in self-calibration (BISC). The RIU interface is represented in the BITSLICE_CONTROL component as shown in the following figure.

Each nibble has its own BITSLICE_CONTROL and therefore its own RIU interface. Two nibbles can be combined in a byte, so a byte can have two RIU interfaces. To allow easy control of both RIU interfaces in a byte, a RIU_OR primitive exists.

The RIU_OR primitive combines both nibble RIU interfaces of a byte into a single RIU interface. The following figure and table show the RIU_OR primitive and its pins. A possible setup joining two nibble RIU into a byte-wide RIU using the RIU_OR primitive is shown in Figure 3. The RIU_NIBBLE_SEL pin of each RIU is used as the MSB address, putting the upper nibble in the upper address space.