Receiver Termination (HP and XP5IO I/O Banks Only) - Receiver Termination (HP and XP5IO I/O Banks Only) - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

The following figure is an example of differential termination for an LVDS (HP I/O), LVDS15 (XP5IO I/O) or LVDS_25 (HD I/O) receiver on a board with 50 Ω transmission lines.

Figure 1. LVDS, LVDS15, or LVDS_25 Receiver Termination

The following figure is an example of internal differential termination for an LVDS receiver on a board with 50 Ω transmission lines.

Figure 2. LVDS with DIFF_TERM Receiver Termination

The following table lists the allowed attributes for the LVDS I/O standards. Support is implied for primitives that are derivatives of the primitives listed in the following table (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to SelectIO IOB Interface Primitives for all supported derivatives.

Table 1. Allowed Attributes for the LVDS I/O Standards
Attributes IBUFDS OBUFDS
HP and XP5IO I/O HD I/O HP and XP5IO I/O HD I/O
Allowed Values Default Allowed Values Default Allowed Values Default Allowed Values Default
IOSTANDARD

LVDS (HP only)

LVDS15 (XP5IO only)

 LVDS_25 (HD only)

LVDS (HP only)

LVDS15 (XP5IO only)

 N/A
DQS_BIAS

TRUE (HP only)

FALSE

FALSE N/A N/A N/A
EQUALIZATION

EQ_LEVEL0

EQ_LEVEL1

EQ_LEVEL2

EQ_LEVEL3

EQ_LEVEL4

EQ_NONE

EQ_NONE N/A N/A N/A N/A
LVDS_PRE_EMPHASIS N/A N/A TRUE FALSE FALSE N/A  
DIFF_TERM

TRUE

FALSE

 FALSE N/A   N/A N/A
DIFF_TERM_ADV

TERM_100

TERM_NONE

 TERM_NONE N/A   N/A N/A
  1. The DQS_BIAS attribute is set on the I/O port rather than the primitive.
  2. The allowed combinations of DQS_BIAS and EQUALIZATION are listed in Table 2.
  3. DQS_BIAS = TRUE is only allowed in AC coupled applications to provide a bias level to VCCO/2 on both P and N sides of the input pin.
  4. LVDS_PRE_EMPHASIS = TRUE is only supported in AC coupled applications.
  5. This attribute must be used with ENABLE_PRE_EMPHASIS to enable the pre-emphasis function.

It is acceptable to have differential inputs such as LVDS, LVDS15, or LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (that is, 1.8V for LVDS outputs). However, these criteria must be met:

  • The optional internal differential termination is not used.
  • DIFF_TERM_ADV = TERM_NONE
  • DIFF_TERM = FALSE (default).
  • The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) .
  • The differential signals at the input pins meet the VIDIFF (min) requirements in the corresponding LVDS or LVDS_25 DC specifications tables of the Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930) .

AC Coupling

Because different banks have different supply levels and input switching thresholds, it can be necessary that an LVDS signal be AC-coupled to a suitable common-mode voltage compatible with the receiver being used. One way to accomplish this criteria is to use an external circuit that both AC-couples and DC-biases the input signals. The following figure shows an example circuit for providing an AC-coupled and DC-biased circuit for a differential clock input. RDIFF provides the 100 Ω differential receiver termination because the internal DIFF_TERM_ADV = TERM_NONE or DIFF_TERM = FALSE.

Figure 3. Example Circuit for AC-Coupled and External DC-Biased Differential Clock Input

HP and XP5IO I/O banks provide an internal bias structure to allow for implementing a bias structure on its LVDS and LVDS15 inputs.

DC_BIAS in HP I/O Banks

HP I/O banks can set a DC bias level to VCCO/2 by setting the DQS_ BIAS attribute to TRUE with an input set to the LVDS IOSTANDARD:

set_property DQS_BIAS TRUE [get_ports <port_name>]
Table 2. Allowed Combinations of DQS_BIAS and EQUALIZATION with LVDS (HP I/O Banks)
Coupling DQS_BIAS Equalization
AC coupling FALSE or TRUE EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4
DC coupling FALSE EQ_NONE

DC_BIAS in XP5IO I/O Banks

XP5IO I/O banks offer more robust options for providing a bias on an AC-coupled link. The DC_BIAS feature creates a bias through an equivalent voltage divider network from the XP5IO I/O bank's VCCO. The DC_BIAS attribute can be added to the XDC:

set_property DC_BIAS DC_BIAS_0|DC_BIAS_1|DC_BIAS_2|DC_BIAS_3 [get_ports port_name]

The DC_BIAS_1 setting provides the equivalent to 192 Ω at 20% VCCO. In a 1.5V bank, the combination of DIFF_TERM_ADV and DC_BIAS_1 provide an appropriate termination and bias for an AC coupled LVDS link without the need for bias or termination components on the PCB. DC_BIAS_2 provides the equivalent of 48 Ω to 20% VCCO, but is not recommended for use with AC coupling due to a higher current draw caused by the voltage divider used to generate the equivalent 48 Ω voltage divider. DC_BIAS_3 provides a 50 Ω to GND bias, which has very limited practical use as a bias network. With an LVDS15 IOSTANDARD used in a 1.5V bank, the combination of DC_BIAS_1 and DIFF_TERM_ADV provide both a bias and termination appropriate for many differential signals that require AC coupling. Because DC_BIAS can corrupt a weaker driver, it should not be used when the IOB is configured as an output or bidirectional.

HD I/O banks do not support any DC bias or equalization settings.