The RX_BITSLICE is the receiver of the RXTX_BITSLICE. For all receive interfaces, RXTX_BITSLICE can be used except where CASCADE delay is needed. RX_BITSLICE allows the two delay lines in the bit slice to be cascaded for a large delay.
Like the RXTX_BITSLICE, the RX_BITSLICE contains an input delay that can continuously be corrected for VT variation by the BITSLICE_CONTROL. High-speed capture registers, deserialization logic for either 1:4 or 1:8, and a shallow FIFO allow easy connection to another clock domain. A block diagram of RX_BITSLICE is shown in the following figure.
The RX_BITSLICE primitive is shown in the following figure. In this figure, black represents inputs and gray represents outputs. Table 1 lists the RXTX_BITSLICE ports.