POD Termination - POD Termination - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

The following figure shows a sample circuit illustrating a unidirectional board topology for POD (1.0V or 1.2V) with matched driver and receiver termination values. Only HP I/O banks support these standards.

Figure 1. POD with Unidirectional Signaling

The following figure shows a sample circuit illustrating a termination technique for POD (1.0V or 1.2V) with bidirectional termination and matched driver and receiver termination values. In a specific circuit, all drivers and receivers must be at the same voltage level (1.0V or 1.2V); they are not interchangeable (that is, POD12 should only interface with POD12).

Figure 2. POD with Bidirectional Signaling