Output Slew Rate Attributes - Output Slew Rate Attributes - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

Many attribute values provide the option of choosing the desired slew rate for I/O output buffers. For LVCMOS, LVTTL, SSTL, HSTL, and HSUL output buffers, including the differential versions, the desired slew rate can be specified with the SLEW attribute.

Although the default SLEW attribute is SLOW, it might be important to specify FAST slew rate for high-performance applications such as high-frequency memory interfaces. However, faster slew rates can also lead to reflections or increased noise issues if not properly designed (such as with terminations, transmission line impedance continuity, and cross-coupling).

The allowed values for the SLEW attribute are SLOW, MEDIUM (HP and XP5IO I/O banks only), or FAST. The SLEW attribute uses the following syntax in the XDC file:

set_property SLEW value [get_ports port_name ]
Note: Not all IOSTANDARDS support all slew options. See Table 2 for available slew options for a given standard.