The following table lists the OSERDESE3 ports.
| Port | I/O | Description |
|---|---|---|
| CLK | Input | High-speed clock input |
| CLKDIV | Input | Low-speed divided clock input |
| D[7:0] | Input | Parallel data inputs for serialization synchronous to CLKDIV |
| OQ | Output | Datapath output |
| RST | Input | Asynchronous reset. |
| T_OUT | Output | 3-state control output to IOB |
| T | Input | 3-state input from internal logic, combinational 3-state T to T_OUT path. A logic High means the data is 3-stated and a logic Low means the data is not 3-stated. |