ODDR with Serialized 3-State - ODDR with Serialized 3-State - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

The ODDRE1 solution in Spartan UltraScale+ devices supports both a single (see the following figure) and a serialized 3-state source shown in the figure next to the following figure.

Figure 1. ODDR with Internal Logic Flip-Flop 3-State
Tip: To achieve required timing constraints for a design set up as in the preceding figure, it might be necessary to LOC the flip-flop in FPGA logic close to the ODDRE1/OSERDESE3 used.

In the single 3-state solution, the flip-flop driving the 3-state is placed in the internal logic with the ODDRE1 placed in a bit slice site. To have the 3-state flip-flop also placed in the same bit slice site as the ODDRE1, the arrangement shown in the following figure can be altered to tie the 3-state D1 and D2 inputs together to a common 3-state.

The following figure shows the serialized ODDRE1 circuit. The SR and C pins of both ODDRE1s must have a common source to allow the implementation software to transform this circuit into a single OSERDESE3 instance that supports the desired function. Although the previously discussed circuit (using ODDRE1 primitives) is preferred, a different way to achieve the discussed circuit is provided in OSERDESE3.

Figure 2. ODDR with ODDR Serialized 3-State