Low-voltage Differential Signaling (LVDS) - Low-voltage Differential Signaling (LVDS) - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English

LVDS is a powerful high-speed interface in many system applications. The I/Os are designed to be compatible with the EIA/TIA electrical specifications for LVDS system and board design. With the use of an LVDS driver (HP and XP5IO I/O banks only) in the IOBs and the optional internal differential termination feature (HP and XP5IO I/O banks only), the need for external source termination in point-to-point applications is eliminated. Spartan UltraScale+ devices provide a flexible solution for creating an LVDS design.

The LVDS I/O standard is only available in the HP I/O banks. It requires a VCCO to be powered at 1.8V for outputs and for inputs when the optional internal differential termination is implemented.

  • DIFF_TERM_ADV = TERM_100
  • DIFF_TERM = TRUE

The LVDS15 I/O standard is only available in the XP5IO I/O banks. It requires a VCCO to be powered at 1.5 V for outputs and for inputs when the optional internal differential termination is implemented.

  • DIFF_TERM_ADV = TERM_100
  • DIFF_TERM = TRUE.
The LVDS_25 I/O standard is available in the HD I/O banks for input-only mode.
Note: HP, XP5IO, and HD I/O banks offer different implementations of an LVDS. Consult the data sheet to ensure compatibility.
Table 1. Available I/O Bank Type
HD HP XP5IO
LVDS_25 (input only) LVDS (1.8V) LVDS15 (1.5V)