Low Voltage Transistor-Transistor Logic (LVTTL) - Low Voltage Transistor-Transistor Logic (LVTTL) - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID
UG861
Release Date
2026-04-28
Revision
1.1 English
Table 1. Available I/O Bank Type
HD HP XP5IO
Available N/A N/A

LVTTL is a general-purpose EIA/JESD standard for 3.3V applications that uses a single-ended CMOS input buffer and a push-pull output buffer. This standard requires a 3.3V output source voltage (VCCO), but does not require the use of a reference voltage (VREF ) or a termination voltage (VTT). This standard is defined by JEDEC (JESD 8C.01).

Sample circuits illustrating both unidirectional and bidirectional LVTTL termination techniques are shown in the following figures. These two diagrams show examples of source-series and parallel terminated topologies.

The following figure shows unidirectional terminated topologies.

Figure 1. LVTTL Unidirectional Termination

The following figure shows a bidirectional, parallel-terminated topology.

Figure 2. LVTTL Bidirectional Termination

The following table details the allowed attributes that can be applied to the LVTTL I/O standard. This standard is only available in the HD I/O banks. Support is implied for primitives that are derivatives of the primitives listed in the following table (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to SelectIO IOB Interface Primitives for all supported derivatives.

Table 2. Allowed Attributes for the LVTTL I/O Standards
Attributes Primitives
IBUF OBUF/OBUFT/IOBUF
Allowed Values Default
IOSTANDARD LVTTL LVTTL
DRIVE N/A 4, 8, or 12 12
SLEW N/A FAST or SLOW SLOW