Low-Voltage Swing Terminated Logic (LVSTL) - Low-Voltage Swing Terminated Logic (LVSTL)

Low-Voltage Swing Terminated Logic (LVSTL) - Low-Voltage Swing Terminated Logic (LVSTL) - UG861

Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)

Document ID

UG861

Release Date

2026-04-28

Revision

1.1 English

The LVSTL standards (LVSTL_11, LVSTL05_10, and LVSTL06_12) are optimized for lower-power memory interfaces. LVSTL06_12 is compatible with LVSTL06 interfaces but is powered at 1.2V while LVSTL05_10 is compatible with LVSTL05 but is powered at 1.0V. LVSTL standards are commonly used for LPDDR4 and LPDDR5 applications. LVSTL standards have receive side termination to ground.

Table 1. Available I/O Bank Type
HD	HP	XP5IO
N/A	N/A	Available

Table 2. LVSTL Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3		OBUF/OBUFT		IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	XP5IO I/O		XP5IO I/O		XP5IO I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	LVSTL_11 LVSTL05_10 LVSTL06_12		LVSTL_11 LVSTL05_10 LVSTL06_12		LVSTL_11 LVSTL05_10 LVSTL06_12
SLEW	N/A		FAST MEDIUM SLOW	SLOW	FAST MEDIUM SLOW	SLOW
ODT	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	N/A		RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE
OUTPUT_IMPEDANCE	N/A		RDRV_40_40 RDRV_48_48¹ RDRV_60_60	RDRV_40_40	RDRV_40_40 RDRV_48_48¹ RDRV_60_60	RDRV_40_40
RDRV_48_48 is not supported in LVSTL_11.